ITF86174SQT
Data Sheet
9A, 30V, 0.016 Ohm, P-Channel, Logic
Level, Power MOSFET
Packaging
TSSOP-8
File Number
4799.3
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.016Ω, VGS = −10V
- rDS(ON) = 0.024Ω, VGS = −4.5V
- rDS(ON) = 0.027Ω, VGS = −4V
• Gate to Source Protection Diode
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
5
1
23
March 2000
4
• Peak Current vs Pulse Width Curve
• Transient Thermal Impedance Curve vs Board Mounting
Area
Symbol
• Switching Time vs RGS Curves
DRAIN(1)
DRAIN(8)
SOURCE(2)
Ordering Information
SOURCE(7)
PART NUMBER
ITF86174SQT
SOURCE(3)
SOURCE(6)
DRAIN(5)
GATE(4)
Absolute Maximum Ratings
PACKAGE
TSSOP-8
BRAND
86174
NOTE: When ordering, use the entire part number. ITF86174SQT2
is available only in tape and reel.
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA = 25oC, VGS = 10V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 25oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
ITF86174SQT
-30
-30
±20
UNITS
V
V
V
9.0
7.0
4.5
4.0
Figure 4
2.0
16
-55 to 150
A
A
A
A
W
mW/oC
oC
300
260
oC
oC
1. TJ = 25oC to 125oC.
2. 62.5oC/W measured using FR-4 board with 1.0in2 (645.2mm2) copper pad at 10s.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. | 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
ITF86174SQT
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-30
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V Figure 11
Zero Gate Voltage Drain Current
IDSS
VDS = -30V, VGS = 0V
-
-
-1
µA
Gate to Source Leakage Current
IGSS
VGS = ±20V
-
-
±10
µA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA Figure 10
-1.0
-
-2.5
V
Drain to Source On Resistance
rDS(ON)
ID = 9.0A, VGS = -10V Figures 8, 9
-
0.012
0.016
Ω
ID = 4.5A, VGS = -4.5V Figure 8
-
0.018
0.024
Ω
ID = 4.0A, VGS = -4.0V Figure 8
-
0.020
0.027
Ω
Pad Area = 1.0 in2 (645.2 mm2) (Note 2)
-
-
62.5
oC/W
Pad Area = 0.035 in2 (22.4 mm2) Figure 20
-
-
165.4
oC/W
Pad Area = 0.0045 in2 (2.88 mm2) Figure 20
-
-
206.8
oC/W
VDD = -15V, ID = 4.5A
VGS = -4.5V,
RGS = 6.8Ω
Figures 14, 18, 19
-
19
-
ns
-
64
-
ns
-
40
-
ns
-
48
-
ns
-
13
-
ns
-
52
-
ns
-
67
-
ns
-
62
-
ns
-
39
-
nC
-
22
-
nC
-
2
-
nC
THERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS VGS = -4.5V
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
SWITCHING SPECIFICATIONS VGS = -10V
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = -15V, ID = 9.0A
VGS = -10V,
RGS = 7.5Ω
Figures 15, 18, 19
tf
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to -10V
Gate Charge at -5V
Qg(-5)
VGS = 0V to -5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -1V
VDD = -15V,
ID = 7.0A,
Ig(REF) = -1.0mA
Figures 13, 16, 17
Gate to Source Gate Charge
Qgs
-
5.7
-
nC
Gate to Drain “Miller” Charge
Qgd
-
8.8
-
nC
-
2000
-
pF
-
475
-
pF
-
215
-
pF
MIN
TYP
MAX
UNITS
ISD = -9.0A
-
-0.8
-
V
trr
ISD = -9.0A, dISD/dt = 100A/µs
-
26
-
ns
QRR
ISD = -9.0A, dISD/dt = 100A/µs
-
14
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = -25V, VGS = 0V,
f = 1MHz
Figure 12
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ITF86174SQT
Typical Performance Curves
POWER DISSIPATION MULTIPLIER
1.2
-10
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
0.2
0
-8
VGS = -10V, RθJA = 62.5oC/W
-6
-4
-2
VGS = -4.0V, RθJA = 187.7oC/W
0
0
25
50
75
100
125
25
150
50
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 62.5oC/W
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
-800
RθJA = 62.5oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
-100
I = I25
125
VGS = -4.0V
-10
150 - TA
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
ITF86174SQT
Typical Performance Curves
-40
RθJA = 62.5oC/W
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
-100
ID, DRAIN CURRENT (A)
-500
ID, DRAIN CURRENT (A)
(Continued)
100µs
-10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
-30
-20
TJ = 150oC
-10
TJ = -55oC
TJ = 25oC
10ms
-1
-1
-10
0
-1.5
-60
-2.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
-3.5
30
VGS = -10V
VGS = -5V
VGS = -4.5V
VGS = -4V
-30
VGS = -3.5V
VGS = -3V
-20
-10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
-3.0
FIGURE 6. TRANSFER CHARACTERISTICS
-40
0
0
-0.5
-1.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = -9A
25
20
ID = -1A
15
10
-1.5
-2
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
-5
-4
-6
-7
-9
-8
-10
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.2
VGS = -10V, ID = -9A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-3
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
VGS = VDS, ID = -250µA
1.4
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-2.5
VGS, GATE TO SOURCE VOLTAGE (V)
1.2
1.0
1.0
0.8
0.8
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ITF86174SQT
Typical Performance Curves
(Continued)
3000
ID = -250µA
1.05
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.10
1.00
0.95
CISS = CGS + CGD
COSS ≅ CDS + CGD
1000
CRSS = CGD
VGS = 0V, f = 1MHz
0.90
-80
-40
0
40
80
120
100
-0.1
160
-1.0
TJ , JUNCTION TEMPERATURE (oC)
-10
-30
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VDD = -15V
200
VGS = -4.5V, VDD = -15V, ID = -4.5A
-8
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
-10
-6
-4
WAVEFORMS IN
DESCENDING ORDER:
ID = -9A
ID = -1A
-2
tf
tr
150
td(OFF)
100
50
td(ON)
0
0
10
20
30
40
0
Qg, GATE CHARGE (nC)
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
300
VGS = -10V, VDD = -15V, ID = -9A
SWITCHING TIME (ns)
250
200
tf
150
td(OFF)
100
tr
50
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
50
ITF86174SQT
Test Circuits and Waveforms
Qgs
VDS
RL
Qgd
VDS
Qg(TH)
0
VGS = -1V
VGS
VGS = -5V
-VGS
VDD
Qg(-5)
+
VGS = -10V
VDD
DUT
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
RL
VDS
-
10%
10%
+
VGS
VDS
0V
DUT
RGS
tf
tr
0
0
90%
90%
10%
-VGS
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
90%
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs Mounting Pad Area
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM , in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be reviewed
to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the TSSOP-8
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
6
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
ITF86174SQT
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 97.5 – 20.2 ×
ln ( Area )
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
240
220
RθJA = 97.5 - 20.2*ln(AREA)
206.8oC/W - 0.0045in2
200
RθJA (oC/W)
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
(EQ. 2)
180
165.4oC/W - 0.035in2
160
140
120
100
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
80
0.001
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
150
COPPER BOARD AREA - DESCENDING ORDER
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
0.04in2
0.28in2
0.52in2
0.76in2
1.00in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
102
103
ITF86174SQT
PSPICE Electrical Model
.SUBCKT ITF86174SQT 2 1 3 ;
REV 14 December 1999
CA 12 8 1.65e-9
CB 15 14 1.65e-9
CIN 6 8 1.82e-9
-
10
DRAIN
2
5
+
8
6
RLDRAIN
RSLC1
51
+
RSLC2
EBREAK 5 11 17 18 -34.95
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
5
51
EBREAK
+
17
18
-
ESLC
-
50
DPLCAP
LGATE
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
9
-
20
21
16
MWEAK
6
18 +
22
DBREAK
MSTRO
DESD1
91
DESD2
11
MMED
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
DBODY
RDRAIN
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
LDRAIN
ESG
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 6 DPLCAPMOD
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.50e-3
RGATE 9 20 3.63
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 7.90e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
18
RVTEMP
CB
6
8
EGS
19
-
-
IT
14
+
+
S1A
S1B
S2A
S2B
17
S2B
13
CA
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2))}
.MODEL DBODYMOD D (IS = 2.75e-12 RS = 4.90e-3 TRS1 = 1.30e-3 TRS2 = -8.50e-6 XTI = 4 IKF = 3.4 CJO = 1.25e-9 TT = 6.5e-10 VJ=0.65 M = 0.43)
.MODEL DBREAKMOD D (RS = 1.50e-1 TRS1 = 1.00e-3 TRS2 = 1.00e-6)
.MODEL DESD1MOD D (BV=18.45 TBV1=-1.43E-3 TBV2=0 RS=200 N=13)
.MODEL DESD2MOD D (BV=18.45 TBV1=-1.43E-3 TBV2=0 RS=200 N=13)
.MODEL DPLCAPMOD D (CJO = 9.05e-10 IS = 1e-30 N=10 VJ=0.372 M = 0.34)
.MODEL MMEDMOD PMOS (VTO = -1.94 KP = 8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.63 RS = 0.1)
.MODEL MSTROMOD PMOS (VTO = -2.20 KP = 65 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u LAMBDA=0.15)
.MODEL MWEAKMOD PMOS (VTO = -1.51 KP = 0.35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36.3 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 7.10e-4 TC2 = -1.02E-6)
.MODEL RDRAINMOD RES (TC1 = 1.60e-2 TC2 = 3.00e-5)
.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = -3.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = 2.10e-3 TC2 = 6.20e-6)
.MODEL RVTEMPMOD RES (TC1 = -5.00e-4 TC2 = 1.20e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 6.2 VOFF= 3.1)
VON = 3.1 VOFF= 6.2)
VON = 1.0 VOFF= -0.5)
VON = -0.5 VOFF= 1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
ITF86174SQT
SABER Electrical Model
REV 14 December 1999
template ITF86174SQT n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.75e-12, cjo = 1.25e-9, tt = 6.5e-10, vj=0.65, m = 0.43, rs = 4.90e-3, trs1 = 1.30e-3, trs2 = -8.50e-6, xti=4, ikf=3.4)
dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1.00e-3, trs2 = 1.00e-6)
dp..desd1mod = (bv=18.45, tbv1=-1.43e-3, tbv2=0, rs=200, nl=13)
dp..desd2mod = (bv=18.45, tbv1=-1.43e-3, tbv2=0, rs=200, nl=13)
dp..model dplcapmod = (cjo = 9.05e-10, isl = 1e-30, nl = 10, vj=0.372, m = 0.34)
m..model mmedmod = (type=_p, vto = -1.94, kp = 8, is = 1e-30, tox = 1, rs=0.1)
m..model mstrongmod = (type=_p, vto = -2.20, kp = 65, is = 1e-30, tox = 1, lambda=0.15)
m..model mweakmod = (type=_p, vto = -1.35, kp = 0.35, is = 1e-30, tox = 1 rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 6.2, voff = 3.1)
LDRAIN
ESG
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 3.1, voff = 6.2)
5
- 8 +
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 1.0, voff = -0.5)
6
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 1.0)
10
c.ca n12 n8 = 1.65e-9
c.cb n15 n14 = 1.65e-9
c.cin n6 n8 = 1.82e-9
RLDRAIN
+
EBREAK 17
18
RSLC1
51
RSLC2
DRAIN
2
-
ISCL
11
dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod
dp.dplcap n10 n6 = model=dplcapmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
RDRAIN
LGATE
i.it n8 n17 = 1
50
DPLCAP
RGATE
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10
RLGATE
EVTHRES
+ 19 8
EVTEMP
-
20
9
MSTRO
DBREAK
CIN
8
DESD2
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
CA
S2A
RBREAK
13
8
15
14
13
S1B
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2))
}
}
19
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = -34.95
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n8 n6 = 1
spe.evtemp n6 n20 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
9
DBODY
MMED
91
res.rbreak n17 n18 = 1, tc1 = 7.10e-4, tc2 = -1.02e-6
res.rdrain n50 n16 = 1.50e-3, tc1 = 1.60e-2, tc2 = 3.00e-5
res.rgate n9 n20 = 3.63
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 2.00e-3, tc2 = -3.00e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 7.90e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -5.00e-4, tc2 = 1.20e-6
res.rvthres n22 n8 = 1, tc1 = 2.10e-3, tc2 = 6.20e-6
MWEAK
6
18 +
22
DESD1
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
16
21
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
ITF86174SQT
SPICE Thermal Model
REV 27 December 1999
ITF86174SQT
Copper Area = 1.0 in2
CTHERM1 th 8 1.5e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 2.0e-2
CTHERM5 5 4 5.0e-2
CTHERM6 4 3 0.2
CTHERM7 3 2 0.5
CTHERM8 2 tl 3.0
JUNCTION
th
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
7
RTHERM1 th 8 0.15
RTHERM2 8 7 0.50
RTHERM3 7 6 1.25
RTHERM4 6 5 8.0
RTHERM5 5 4 12.0
RTHERM6 4 3 12.0
RTHERM7 3 2 18.0
RTHERM8 2 tl 25.0
CTHERM3
RTHERM3
6
RTHERM4
CTHERM4
5
SABER Thermal Model
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 1.5e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 2.0e-2
ctherm.ctherm5 5 4 = 5.0e-2
ctherm.ctherm6 4 3 = 0.2
ctherm.ctherm7 3 2 = 0.5
ctherm.ctherm8 2 tl = 3.0
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
2
rtherm.rtherm1 th 8 = 0.15
rtherm.rtherm2 8 7 = 0.50
rtherm.rtherm3 7 6 = 1.25
rtherm.rtherm4 6 5 = 8.0
rtherm.rtherm5 5 4 = 12.0
rtherm.rtherm6 4 3 = 12.0
rtherm.rtherm7 3 2 = 18.0
rtherm.rtherm8 2 tl = 25.0
}
CTHERM8
RTHERM8
tl
CASE
TABLE 1. THERMAL MODELS
0.04in2
0.28in2
0.52in2
0.76in2
1.0in2
CTHERM6
0.12
0.20
0.28
0.19
0.20
CTHERM7
0.25
0.48
0.45
0.39
0.50
CTHERM8
1.3
2.3
2.2
2.7
3.0
RTHERM6
26
20
15
11
12
RTHERM7
39
24
21
21
18
RTHERM8
49.5
36.8
39
29.5
25
COMPONENT
10
ITF86174SQT
MO-153AA (TSSOP-8)
8 LEAD JEDEC MO-153AA TSSOP PLASTIC PACKAGE
E
INCHES
A
E1
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.041
0.047
1.05
1.20
-
A1
0.002
0.006
0.05
0.15
-
b
0.010
0.012
0.25
0.30
-
8
A1
e
D
c
0.127
-
4
5
0.005
b
c
D
0.114
0.122
2.90
3.10
2
E
0.244
0.260
6.20
6.60
-
E1
0.170
0.177
4.30
4.50
3
e
0.004 IN
0.10mm
L
0o-8o
0.015
0.4
0.035
0.9
0.025
0.65
0.232
5.9
0.077
1.95
L
0.025 BSC
0.020
0.028
0.65 BSC
0.50
0.70
4
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC MO-153AA outline dated 10-97.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. Controlling dimension: Millimeter
6. Revision 2 dated: 1-00.
MO-153AA (TSSOP-8)
12mm TAPE AND REEL
20.4mm
1.5mm
DIA. HOLE
4.0mm
2.0mm
13mm
1.75mm
CL
12mm
330mm
53.5mm
8.0mm
13.4mm
USER DIRECTION OF FEED
COVER TAPE
GENERAL INFORMATION
1. 3000 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
11
ITF86174SQT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
12
EUROPE
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