ITF86182SK8T
Data Sheet
11A, 30V, 0.0115 Ohm, P-Channel, Logic
Level, Power MOSFET
January 2000
File Number
4797.2
Features
• Ultra Low On-Resistance
[ /Title
- rDS(ON) = 0.0115Ω, VGS = −10V
Packaging
(ITF86
- rDS(ON) = 0.016Ω, VGS = −4.5V
SO8 (JEDEC MS-012AA)
- rDS(ON) = 0.0175Ω, VGS = −4V
182SK
BRANDING DASH
8T)
• Gate to Source Protection Diode
/Sub• Simulation Models
ject
- Temperature Compensated PSPICE™ and SABER
5
(11A,
Electrical Models
30V,
Spice and SABER Thermal Impedance Models
1
2
- www.intersil.com
0.0115
3
4
Ohm,
• Peak Current vs Pulse Width Curve
P• Transient Thermal Impedance Curve vs Board Mounting
ChanArea
Symbol
nel,
• Switching Time vs RGS Curves
Logic
SOURCE(1)
DRAIN(8)
Level,
Ordering Information
Power
SOURCE(2)
DRAIN(7)
PART NUMBER
PACKAGE
BRAND
MOSITF86182SK8T
SO8
86182
FET)
NOTE: When ordering, use the entire part number. ITF86182SK8T
SOURCE(3)
DRAIN(6)
/Author
is available only in tape and reel.
DRAIN(5)
()
GATE(4)
/Keywords
(InterITF86182SK8T
UNITS
sil,
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
-30
V
SemiDrain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
-30
V
conduc- Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
tor, PDrain Current
Continuous (TA= 25oC, VGS = 10V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
-11.0
A
ChanContinuous (TA= 25oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
-9.0
A
nel,
Continuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
-6.0
A
Logic
Continuous (TA= 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
-6.0
A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Figure 4
Level
2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
2.5
W
Power Power Dissipation (Note
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
mW/oC
MOSoC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 150
FET,
Maximum Temperature for Soldering
oC
SO8)
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
300
Package Body for 10s, See Tech brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
260
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 10 second.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc.http://www.intersil.com or 321-727-9207 | Copyright © Intersil Corporation 2000
ITF86182SK8T
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ITF86182SK8TOFF STATE SPECIFICATIONS
-30
-
-
V
Zero Gate Voltage Drain Current
IDSS
VDS = -30V, VGS = 0V
-
-
-1
µA
Gate to Source Leakage Current
IGSS
VGS = ±20V
-
-
±10
uA
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V Figure 11
ITF86182SK8TON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA Figure 10
-1.0
-
-2.5
V
Drain to Source On Resistance
rDS(ON)
ID = -11.0A, VGS = -10V Figures 8, 9
-
0.0085
0.0115
Ω
ID = -6.0A, VGS = -4.5V Figure 8
-
0.011
0.016
Ω
ID = -6.0A, VGS = -4.0V Figure 8
-
0.012
0.0175
Ω
Pad Area = 0.76 in2 (490.3 mm2) (Note 2)
-
-
50
oC/W
Pad Area = 0.054 in2 (34.8 mm2) Figure 20
-
-
152
oC/W
Pad Area = 0.0115 in2 (7.42 mm2) Figure 20
-
-
189
oC/W
-
20
-
ns
-
80
-
ns
-
70
-
ns
-
80
-
ns
-
16
-
ns
-
85
-
ns
-
100
-
ns
-
105
-
ns
-
67
-
nC
-
37
-
nC
-
3.4
-
nC
ITF86182SK8TTHERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient
RθJA
ITF86182SK8TSWITCHING SPECIFICATIONS (VGS = -4.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = -15V, ID = -6.0A
VGS = -4.5V,
RGS = 4.9Ω
Figures 14, 18, 19
tf
ITF86182SK8TSWITCHING SPECIFICATIONS (VGS = -10V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = -15V, ID = -11.0A
VGS = -10V,
RGS = 4.9Ω
Figures 15, 18, 19
tf
ITF86182SK8TGATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to -10V
Gate Charge at -5V
Qg(-5)
VGS = 0V to -5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -1V
VDD = -15V,
ID = -6.0A,
Ig(REF) = -1.0mA
Figures 13, 16, 17
Gate to Source Gate Charge
Qgs
-
8
-
nC
Gate to Drain “Miller” Charge
Qgd
-
13.5
-
nC
-
3375
-
pF
-
790
-
pF
-
375
-
pF
MIN
TYP
MAX
UNITS
ITF86182SK8TCAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = -25V, VGS = 0V,
f = 1MHz
Figure 12
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ISD = -6.0A
-
-0.8
-
V
trr
ISD = -6.0A, dISD/dt = 100A/µs
-
33
-
ns
QRR
ISD = -6.0A, dISD/dt = 100A/µs
-
20
-
nC
ITF86182SK8T
Typical Performance Curves
-12
VGS = -10V, RθJA = 50oC/W
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
-9
-6
-3
VGS = -4.0V, RθJA = 189oC/W
0.2
0
0
0
25
50
75
100
125
25
150
50
TA , AMBIENT TEMPERATURE (oC)
3
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
75
100
120
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
0.1
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-1000
IDM, PEAK CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
RθJA = 50oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
-100
125
VGS = -4.5V
-10
150 - TA
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
ITF86182SK8T
Typical Performance Curves
-300
-40
ID, DRAIN CURRENT (A)
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
-100
ID, DRAIN CURRENT (A)
(Continued)
RθJA = 50oC/W
100µs
-10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
-30
-20
TJ = 150oC
-10
TJ = 25oC
-1
0
-1
-10
-100
-1
-1.5
-2.0
-2.5
VGS, GATE TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
25
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = -10V
VGS = -5V
-30
VGS = -4.5V
VGS = -3.5V
-20
VGS = -3V
-10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
0
0
-0.2
-0.4
-0.6
-0.8
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = -11A
20
15
ID = -2A
10
5
-2
-1
-4
-6
-8
-10
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.6
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = -250µA
1.4
1.2
VGS = -10V, ID = -11A
1.0
NORMALIZED GATE
THRESHOLD VOLTAGE
ID, DRAIN CURRENT (A)
-3.0
FIGURE 6. TRANSFER CHARACTERISTICS
-40
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
TJ = -55oC
10ms
1.0
0.8
0.6
0.8
0.4
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ITF86182SK8T
(Continued)
1.10
5000
CISS = CGS + CGD
ID = -250µA
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
Typical Performance Curves
1.05
1.0
0.95
COSS ≅ CDS + CGD
1000
300
-80
-40
0
40
80
120
160
-0.1
-1
TJ , JUNCTION TEMPERATURE (oC)
-10
-30
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-10
400
VDD = -15V
VGS = -4.5V, VDD = -15V, ID = -6A
tr
-8
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
CRSS = CGD
VGS = 0V, f = 1MHz
0.90
-6
-4
WAVEFORMS IN
DESCENDING ORDER:
ID = -11A
ID = -2A
-2
0
0
15
30
45
60
300
tf
200
td(OFF)
100
td(ON)
0
0
75
10
Qg, GATE CHARGE (nC)
20
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
500
SWITCHING TIME (ns)
VGS = -10V, VDD = -15V, ID = -11A
td(OFF)
400
tf
300
200
tr
100
td(ON)
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (W)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
40
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
0
30
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
50
ITF86182SK8T
Test Circuits and Waveforms
Qgs
VDS
RL
Qgd
VDS
Qg(TH)
0
VGS= -1V
VGS
VGS= -5V
-VGS
VDD
Qg(-5)
+
VGS= -10V
VDD
DUT
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
RL
VDS
-
10%
10%
+
VGS
VDS
0V
DUT
RGS
tf
tr
0
0
90%
90%
10%
-VGS
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
90%
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------R θJA
(EQ. 1)
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
6
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
ITF86182SK8T
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
R θJA = 83.2 – 23.6 ×
ln ( Area )
(EQ. 2)
240
RθJA = 83.2 - 23.6*ln(AREA)
200
RθJA (oC/W)
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
189oC/W - 0.0115in2
152oC/W - 0.054in2
160
120
80
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
150
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL RESISTANCE vs MOUNTING PAD AREA
7
102
103
ITF86182SK8T
PSPICE Electrical Model
.SUBCKT ITF86182SK8 2 1 3 ;
REV Nov 1999
CA 12 8 2.2e-9
CB 15 14 2.6e-9
CIN 6 8 2.9e-9
LDRAIN
ESG
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 6 DPLCAPMOD
DRAIN
2
5
+
8
6
RLDRAIN
RSLC1
51
+
RSLC2
5
51
EBREAK 5 11 17 18 -36.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EBREAK
-
ESLC
9
-
20
DBODY
RDRAIN
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
21
16
MWEAK
6
18 +
22
DBREAK
MSTRO
DESD1
91
DESD2
11
MMED
RLGATE
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.3e-3
RGATE 9 20 4.3
RLDRAIN 2 5 10
RLGATE 1 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
-
IT
14
+
+
S1A
S1B
S2A
S2B
+
17
18
50
DPLCAP
LGATE
IT 8 17 1
-
10
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*220),2.1))}
.MODEL DBODYMOD D (IS = 1.1e-11 N = 1.03 RS = 5e-3 TRS1 = 1.75e-3 TRS2 = 5.08e-6 CJO = 2.17e-9 TT = 1e-10 M = 0.5)
.MODEL DBREAKMOD D (RS = 1.9e-1 TRS1 = 1e-4 TRS2 = -1e-6)
.MODEL DESD1MOD D (BV = 17.2 TBV1 = -2.5E-3 N = 21 RS = 500)
.MODEL DESD2MOD D (BV = 17 TBV1 = -2.5E-3 N = 21 RS = 0)
.MODEL DPLCAPMOD D (CJO = 1.6e-9 IS = 1e-30 N = 10 M = 0.37 VJ = 0.44)
.MODEL MMEDMOD PMOS (VTO = -1.47 KP = 4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4.3)
.MODEL MSTROMOD PMOS (VTO = -1.82 KP = 87 LAMBDA = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD PMOS (VTO = -1.19 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 43 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 7.3e-4 TC2 = -8e-7)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1e-6)
.MODEL RSLCMOD RES (TC1 = 2e-4 TC2 = -2e-5)
.MODEL RSOURCEMOD RES (TC1 = 8e-4 TC2 = 1e-5)
.MODEL RVTHRESMOD RES (TC1 = 1.5e-3 TC2 = 4.1e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.2e-3 TC2 = -1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 2.5 VOFF= 1.5)
VON = 1.5 VOFF= 2.5)
VON = 0.75 VOFF= -0.5)
VON = -0.5 VOFF= 0.75)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
ITF86182SK8T
SABER Electrical Model
REV Nov 1999
template itf86182sk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.1e-11, nl = 1.03, cjo = 2.17e-9, tt = 1e-10, m = 0.5, rs = 5e-3, trs1 = 1.75e-3, trs2 = 5.08e-6)
dp..model dbreakmod = (rs = 1.9e-1, trs1 = 1e-4, trs2 = -1e-6)
dp..model desd1mod = (bv = 17.2, nl = 21, rs = 500)
dp..model desd2mod = (bv = 17, nl = 21, rs = 0)
dp..model dplcapmod = (cjo = 1.6e-9, isl = 10e-30, nl = 10, m = 0.37, vj = 0.44)
m..model mmedmod = (type=_p, vto = -1.47, kp = 4, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_p, vto = -1.82, kp = 87, lambda = 0.01, is = 1e-30, tox = 1)
m..model mweakmod = (type=_p, vto = -1.19, kp = 0.06, is = 1e-30, tox = 1)
ESG
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5)
5
- 8 +
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5)
6
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.75, voff = -0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.75)
+
10
RSLC1
51
c.ca n12 n8 = 2.2e-9
c.cb n15 n14 = 2.6e-9
c.cin n6 n8 = 2.9e-9
LDRAIN
DRAIN
2
RLDRAIN
EBREAK 17
18
RSLC2
-
ISCL
11
dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
dp.dplcap n10 n6 = model=dplcapmod
DBREAK
RDRAIN
LGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10
RLGATE
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
i.it n8 n17 = 1
50
DPLCAP
-
20
9
16
21
MWEAK
6
18 +
22
MSTRO
DESD1
LSOURCE
CIN
91
8
DESD2
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 7.3e-4, tc2 = -8e-7
res.rdrain n50 n16 = 2.3e-3, tc1 = 1e-2, tc2 = 1e-6
res.rgate n9 n20 = 4.3
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 2e-4, tc2 = -2e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4e-3, tc1 = 8e-4, tc2 = 1e-5
res.rvtemp n18 n19 = 1, tc1 = -1.2e-3, tc2 = -1e-6
res.rvthres n22 n8 = 1, tc1 = 1.5e-3, tc2 = 4.1e-6
DBODY
MMED
7
RSOURCE
RLSOURCE
S1A
12
CA
S2A
RBREAK
13
8
15
14
13
S1B
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n5 n11 n17 n18 = -36.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n8 n6 = 1
spe.evtemp n6 n20 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/220))** 2.1))
}
}
9
SOURCE
3
ITF86182SK8T
SPICE Thermal Model
REV April 1999
ITF86182SK8
Copper Area = 0.76 in2
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2.0e-1
CTHERM7 3 2 1
CTHERM8 2 tl 3
th
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 13
RTHERM7 3 2 19
RTHERM8 2 tl 29.7
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
CTHERM4
5
Copper Area = 0.76 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 2.0e-1
ctherm.ctherm7 3 2 = 1
ctherm.ctherm8 2 tl = 3
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 13
rtherm.rtherm7 3 2 = 19
rtherm.rtherm8 2 tl = 29.7
}
2
CTHERM8
RTHERM8
tl
AMBIENT
TABLE 1. Thermal Models
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONENT
10
ITF86182SK8T
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E1
INCHES
A
A1
1
e
2
6
D
5
b
SYMBOL
c
0.004 IN
0.10 mm
L
0o-8o
0.060
1.52
0.050
1.27
0.024
0.6
0.155
4.0
0.275
7.0
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
h x 45o
MIN
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
2.0mm
USER DIRECTION OF FEED
1.75mm
CL
MS-012AA
12mm
12mm TAPE AND REEL
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
11
50mm
12.4mm
ITF86182SK8T
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Intersil Corporation
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TEL: (321) 724-7000
FAX: (321) 724-7240
12
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