SHENZHENFREESCALE SIHD7N60E

SiHD7N60E
E Series Power MOSFET
FEATURES
•
•
•
•
•
•
PRODUCT SUMMARY
Low Figure-of-Merit (FOM) Ron x Qg
Low Input Capacitance (Ciss)
Reduced Switching and Conduction Losses
Ultra Low Gate Charge (Qg)
Avalanche Energy Rated (UIS)
Material categorization: For definitions of
compliance please see www.freescale.net.cn
VDS (V) at TJ max.
650
RDS(on) max. at 25 °C (Ω)
VGS = 10 V
0.6
Qg max. (nC)
40
Qgs (nC)
5
Qgd (nC)
9
Configuration
Single
APPLICATIONS
•
•
•
•
Server and Telecom Power Supplies
Switch Mode Power Supplies (SMPS)
Power Factor Correction Power Supplies (PFC)
Lighting www.freescale.net.cn
- High-Intensity Discharge (HID)
- Fluorescent Ballast Lighting
• Industrial
- Welding
- Induction Heating
- Motor Drives
- Battery Chargers
- Renewable Energy
- Solar (PV Inverters)
D
DPAK
(TO-252)
D
G
G
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
SiHD7N60E-GE3
SiHD7N60ET-GE3
Lead (Pb)-free and Halogen-free
SiHD7N60ETR-GE3
SiHD7N60ETL-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Gate-Source Voltage AC (f > 1 Hz)
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
Linear Derating Factor
LIMIT
UNIT
600
V
± 20
30
7
5
A
18
0.63
W/°C
Single Pulse Avalanche Energyb
EAS
43
mJ
Maximum Power Dissipation
PD
78
W
TJ, Tstg
- 55 to + 150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dtd
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 13.8 mH, Rg = 25 Ω, IAS = 2.5 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
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dV/dt
37
3
300c
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V/ns
°C
SiHD7N60E
E Series Power MOSFET
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
1.6
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.68
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
nA
VGS = ± 20 V
-
-
± 100
VDS = 600 V, VGS = 0 V
-
-
1
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
10
IGSS
IDSS
μA
-
0.5
0.6
Ω
gfs
VDS = 50 V, ID = 3.5 A
-
1.9
-
S
Input Capacitance
Ciss
680
-
Coss
-
39
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
5
-
Effective Output Capacitance, Energy
Relateda
Co(er)
-
34
-
Effective Output Capacitance, Time
Relatedb
Co(tr)
-
100
-
Qg
-
20
40
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = 10 V
ID = 3.5 A
Dynamic
Total Gate Charge
pF
VDS = 0 V to 480 V, VGS = 0 V
Gate-Source Charge
Qgs
-
5
-
Gate-Drain Charge
Qgd
-
9
-
Turn-On Delay Time
td(on)
-
13
26
tr
VDD = 480 V, ID = 3.5 A,
VGS = 10 V, Rg = 9.1 Ω
-
13
26
-
24
48
-
14
28
f = 1 MHz, open drain
-
1.1
-
-
-
7
S
-
-
28
TJ = 25 °C, IS = 3.5 A, VGS = 0 V
-
-
1.2
-
230
-
ns
TJ = 25 °C, IF = IS = 3.5 A,
dI/dt = 100 A/μs, VR = 20 V
-
1.9
-
μC
-
14
-
A
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 3.5 A, VDS = 480 V
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
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V
SiHD7N60E
E Series Power MOSFET
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
16
12
3
TJ = 25 °C
ID = 3.5 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
20
8
4
2.5
2
1.5
1
0.5
0
- 60 - 40 - 20 0
0
0
5
10
15
20
25
30
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
10 000
TJ = 150 °C
Capacitance (pF)
ID, Drain-to-Source Current (A)
TOP
6
Ciss
1000
100
Crss
10
1
0
0
5
10
15
20
25
30
0
VDS, Drain-to-Source Voltage (V)
200
100
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
24
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
3
TJ = 25 °C
16
12
TJ = 150 °C
8
4
VDS = 480 V
VDS = 300 V
VDS = 120 V
20
16
12
8
4
0
0
0
3/9
20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
12
9
VGS = 10 V
5
10
15
20
25
0
10
20
30
40
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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SiHD7N60E
E Series Power MOSFET
8
TJ = 150 °C
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
100
TJ = 25 °C
10
1
6
4
2
VGS = 0 V
0
0.1
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
25
VSD, Source-Drain Voltage (V)
IDM = Limited
Limited by RDS(on)*
1 ms
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
700
675
650
625
600
575
550
BVDSS Limited
10
100
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is s
525
- 60 - 40 - 20 0
1000
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Maximum Safe Operating Area
Normalized Effective Transient
Thermal Impedance
150
725
VDS, Drain-to-Source
Brakdown Voltage (V)
ID, Drain Current (A)
125
750
Operation in this Area
Limited by RDS(on)
100 μs
0.01
1
100
Fig. 9 - Maximum Drain Current vs. Case Temperature
10
1
75
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
50
Fig. 10 - Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
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SiHD7N60E
E Series Power MOSFET
RD
V DS
QG
10 V
V GS
D.U.T.
RG
QGS
+
- V DD
QGD
VG
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
Charge
Fig. 16 - Basic Gate Charge Waveform
Fig. 12 - Switching Time Test Circuit
Current regulator
Same type as D.U.T.
V DS
90 %
50 kΩ
12 V
0.2 μF
0.3 μF
+
10 %
V GS
D.U.T.
td(on)
td(off)
tr
tf
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
Vary t p to obtain
required IAS
VDS
D.U.T.
RG
+
-
I AS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
V DS
tp
V DD
V DS
IAS
Fig. 15 - Unclamped Inductive Waveforms
5/9
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SiHD7N60E
E Series Power MOSFET
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
6/9
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SiHD7N60E
E Series Power MOSFET
TO-252AA (HIGH VOLTAGE)
E
b3
E1
L3
D1
D
H
L4
b2
b
A
c2
e
A1
L1
L
c
θ
L2
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
E
6.40
6.73
0.252
0.265
L
1.40
1.77
0.055
L1
2.743 REF
L2
0.070
0.108 REF
0.508 BSC
0.020 BSC
L3
0.89
1.27
0.035
0.050
L4
0.64
1.01
0.025
0.040
D
6.00
6.22
0.236
0.245
H
9.40
10.40
0.370
0.409
b
0.64
0.88
0.025
0.035
b2
0.77
1.14
0.030
0.045
b3
5.21
5.46
0.205
e
2.286 BSC
0.215
0.090 BSC
A
2.20
2.38
0.087
A1
0.00
0.13
0.000
0.094
0.005
c
0.45
0.60
0.018
0.024
c2
0.45
0.58
0.018
0.023
D1
5.30
-
0.209
-
E1
4.40
-
0.173
-
θ
0'
10'
0'
10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
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SiHD7N60E
E Series Power MOSFET
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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SiHD7N60E
E Series Power MOSFET
Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“freestyle”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. All
operating parameters, including typical pa rameters, must be validated for each customer application by the customer’s
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Material Category Policy
freestyle Intertechnology, Inc. hereby certi fies that all its products that are id entified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
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Please note that some freestyle documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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