SAMSUNG S3C7324

S3C7324/P7324
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 4-channel A/D converter, 24-bit AM/FM frequency counter and
watch timer, the S3C7324 offers an excellent design solution for a wide variety of applications that require LCD
functions and audio applications.
Up to 32 pins of the 64-pin QFP package, it can be dedicated to I/O. Five vectored interrupts provide fast
response to internal and external events. In addition, the S3C7324 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7324 microcontroller is also available in OTP (One Time Programmable) version, S3P7324 . The
S3P7324 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7324 is comparable to S3C7324, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7324/P7324
FEATURES
Memory
Bit Sequential Carrier
— 256 × 4-bit RAM
— Support 16-bit serial data transfer in arbitrary
format
— 4096 × 8-bit ROM
Interrupts
I/O Pins
— Two internal vectored interrupts
— Input only: 8 pins
— Three external vectored interrupts
— I/O: 16 pins
— Two quasi-interrupts
— Output only: 8 pins sharing with segment driver
outputs
Memory-Mapped I/O Structure
— Data memory bank 15
LCD Controller/Driver
— Maximum 14-digit LCD direct drive capability
Two Power-Down Modes
— 28 segment and 4 common pins
— Idle mode (only CPU clock stops)
— Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
— Stop mode (main system clock stops)
— Subsystem clock stops
— Internal resistor circuit for LCD bias
Oscillation Sources
8-Bit Basic Timer
— Crystal, ceramic, or RC for main system clock
— Programmable interval timer
— Crystal or external oscillator for subsystem clock
— Watchdog timer
— Main system clock frequency: 4.19 MHz (typical)
8-Bit Timer
— Programmable 8-bit timer
Watch Timer
— Real-time and interval time measurement
— Four frequency outputs to BUZ pin
— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)
— Clock source generation for LCD
Operating Temperature
24-Bit Frequency Counter (FC)
— – 40 °C to 85 °C
— Level = 300mVpp (Min.)
— AMF input range = 0.5 MHz to 10 MHz
— FMF input range = 30 MHz to 150 MHz
A/D Converter
— 4-channels with 8-bit resolution
— 17 µs (Min.) conversion speed
1-2
Operating Voltage Range
— 1.8 V to 5.5 V at 3 MHz
— 3.0 V to 5.5 V at FC mode
Package Type
— 64-pin QFP
S3C7324/P7324
PRODUCT OVERVIEW
BLOCK DIAGRAM
X IN XTIN
X OUT XTOUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
I/O Port 1
P5.0-P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
Clock
Input
Port 2
Input
Port 3
A/D
Converter
P4.0-P4.3
Interrupt
Control
Block
I/O
Port 4, 5
Internal
Interrupts
Instruction Decoder
Arithmetic
and
Logic Unit
Watchdog
Timer
Instruction
Register
Program
Counter
Basic
Timer
Freq.
Counter
Watch
Timer
FMF
AMF
8-Bit
Timer
Program
Status Word
LCD Driver/
Countroller
Stack
Pointer
Output
Port 8,9
COM0-COM3
SEG0-SEG19
P8.0-P8.3/
SEG27-SEG24
P9.0-P9.3/
SEG23-SEG20
I/O Port 6
256 x 4-Bit
Data
Memory
4-Kbyte
Program
Memory
Figure 1-1. S3C7324 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7324/P7324
64
63
62
61
60
59
58
57
56
55
54
53
52
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S3C7324
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.3/INT4
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
20
21
22
23
24
25
26
27
28
29
30
31
32
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
VDD
V SS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
Figure 1-2. S3C7324 64-QFP Pin Assignment
1-4
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/ SEG20
P9.2/ SEG21
P9.1/SEG22
P9.0/ SEG23
P8.3/ SEG24
P8.2/ SEG25
P8.1/SEG26
P8.0/ SEG27
S3C7324/P7324
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7324 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
P1.0
P1.1
P1.2
P1.3
I/O
4-bit I/O port.
1-bit or 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
17
18
19
20
INT0
INT1
INT2
INT4
Input
D-4
P2.0
P2.1
P2.2
P2.3
I
4-bit input port. 1-bit and 4-bit read and
test are possible.
Pull-up resistors can be configured by
software.
1
2
3
4
–
–
FMF
AMF
Input
A-4
A-4
B-4
B-4
P3.0
P3.1
P3.2
P3.3
I
4-bit input port.
1-bit and 4-bit read and test are possible
Pull-up resistors can be configured by
software.
5
6
7
8
ADC0
ADC1
ADC2
ADC3
Input
F-13
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports. N-channel open-drain
output up to 5 V. 1-bit and 4-bit read,
write, and test are possible. Ports 4 and
5 can be paired to support 8-bit data.
Pull-up resistors can be configured by
software.
21–24
25–28
–
–
Input
E-2
P6.0
P6.1
P6.2
P6.3
I/O
1-bit and 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
29
30
31
32
BUZ
KS0
KS1
KS2
Input
D-2
D-4
D-4
D-4
SEG0–SEG19
O
LCD segment signal output
60–41
–
Output
H-16
P8.0–P8.3
P9.0–P9.3
O
4-bit output ports. 1-bit and 4-bit write
and test are possible. Ports 8 and 9 can
be paired to support 8-bit data.
33–36
37–40
SEG27–
SEG20
Output
H-16
COM0–COM3
O
LCD common signal output
64–61
–
Output
H-16
VDD
–
Main power supply
9
–
–
–
VSS
–
Main ground
10
–
–
–
XOUT, XIN
–
Crystal, ceramic, or RC oscillator pins for
main system clock. (For external clock
input, use XIN and input XIN's reverse
phase to XOUT)
11,12
–
–
–
XTOUT, XTIN
–
Crystal oscillator pin for a subsystem
clock. (For external clock input, use XTIN
and input XTIN's reverse phase to
XTOUT)
15,14
–
–
–
1-5
PRODUCT OVERVIEW
S3C7324/P7324
Table 1-1. S3P7324 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
SEG20–SEG27
O
LCD segment signal output
40–33
P9.0–P9.3
P8.0–P8.3
Output
H-16
ADC0–ADC3
I
ADC input ports
5–8
P3.0–P3.3
Input
F-13
FMF
AMF
I
External FM/AM frequency inputs
3
4
P2.2
P2.3
Input
B-4
INT4
I
External interrupt input with detection of
rising or falling edges.
20
P1.3
Input
A-4
INT2
I
Quasi-interrupt with detection of rising
edge signals.
19
P1.2
Input
A-4
INT1
INT0
I
External interrupt. The triggering edges
for INT0 and INT1 are able to be
selected. Only INT0 is synchronized with
the system clock.
18
17
P1.1
P1.0
Input
A-4
BUZ
O
2, 4, 8, or 16 kHz frequency output for
buzzer sound with 4.19 MHz main
system clock.
29
P6.0
Input
D-2
KS0–KS2
I
Quasi-interrupt input with falling edge
detection.
30–32
P6.1–P6.3
Input
D-4
RESET
I
System reset signal
16
–
Input
B
TEST
–
System test pin(must be connected to
VSS)
13
–
–
–
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
1-6
S3C7324/P7324
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-CHANNEL
IN
IN
N-CHNNEL
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
Type A
Feedback
Enable
Pull-up
Enable
In
Figure 1-4. Pin Circuit Type A-4
Pull-down
Enable
Figure 1-6. Pin Circuit Type B-4
1-7
PRODUCT OVERVIEW
S3C7324/P7324
VDD
VDD
Pull-up
Enable
Data
Out
Data
Output
Disable
Output
Disable
Figure 1-7. Pin Circuit Type C
VDD
PNE
Pull-up
Enable
I/O
Circuit
TYPE C
I/O
Figure 1-8. Pin Circuit Type D-2
1-8
VDD
Data
Pull-up
Enable
Output
Disable
I/O
Figure 1-9. Pin Circuit Type D-4
VDD
Data
Circuit
TYPE C
Output
Disable
Figure 1-10. Pin Circuit Type E-2
S3C7324/P7324
PRODUCT OVERVIEW
VDD
Pull-up Enable
Data
In
ADCEN
ADC Select
To ADC
Figure 1-11. Pin Circuit Type F-13
1-9
PRODUCT OVERVIEW
S3C7324/P7324
VDD
VLC0
VLC1
SEG/COM
and Port Data
VLC2
Figure 1-12. Pin Circuit Type H-16
1-10
Out
S3C7324/P7324
15
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7324 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— Input timing for RESET
— Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
15-1
ELECTRICAL DATA
S3C7324/P7324
Table 15-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Supply Voltage
VDD
–
Input Voltage
VIN
Output Voltage
VO
Output Current High
I OH
I OL
Output Current Low
Rating
Units
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
All I/O ports
– 0.3 to VDD + 0.3
–
One I/O port active
– 15
mA
All I/O ports active
– 30
One I/O port active
+ 30 (Peak value)
+ 15 (note)
Total value for ports 1, 4, 5 and 6
+ 100 (Peak value)
+ 60
Operating Temperature
Storage Temperature
(note)
TA
–
– 40 to + 85
Tstg
–
– 65 to + 150
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ×
°C
Duty .
Table 15-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input high
voltage
Input low
voltage
Output high
voltage
15-2
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those
specified below
0.7 VDD
VIH2
P1, P3, RESET, P2.0−1 and
P6.1−3
0.8 VDD
VDD
VIH3
XIN, XOUT, XTIN, and XTOUT
VDD – 0.1
VDD
VIL1
All input pins except those
specified below
VIL2
P1, P3, RESET, P2.0−1 and
P6.1−3
0.2 VDD
VIL3
XIN, XOUT, XTIN, and XTOUT
0.1
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 1, 4, 5, and 6
VDD – 1.0
VOH2
VDD = 4.5 V to 5.5 V
IOH = –100 µA Port 8 and 9
VDD – 2.0
–
–
–
0.3 VDD
–
V
V
S3C7324/P7324
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 1, 4, 5, and 6
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL = 100 µA ; Ports 8and 9
–
–
1
Input high
leakage
current (note)
ILIH1
VIN = VDD
All input pins
–
–
3
Input low
leakage
current (note)
ILIL1
VIN = 0 V
All input pins
–
–
–3
Output high
leakage
current (note)
ILOH1
VOUT = VDD
All output pins
–
–
3
Output low
leakage
current (note)
ILOL
VOUT = 0 V
All output pins
Pull-up
resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
20
40
80
VDD = 3 V
30
95
200
VIN = 0 V; VDD = 5 V
100
230
400
200
480
800
Output low
voltage
RL2
µA
–3
KΩ
RESET
VDD = 3 V
NOTE:
Except for XIN, XOUT, XTIN, and XTOUT
15-3
ELECTRICAL DATA
S3C7324/P7324
Table 15-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
LCD voltage
dividing
resistor
RLCD
COM output
RCOM
RSEG
COM output
voltage
deviation
VDC
SEG output
voltage
deviation
VDS
15-4
VDD = 5 V
Typ
Max
Units
60
84
130
KΩ
−
3
6
5
15
VDD = 5 V
3
6
5
15
–
± 45
± 90
–
± 45
± 90
–
VDD = 3 V
impedance
Oscillator
feedback
resistor
TA = 25 øC
Min
VDD = 3 V
impedance
SEG output
Conditions
VDD = 5 V (VLC0-COMi)
mV
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (I = 0–27)
ROSC1
VDD = 5.0 V; TA = 25; XIN = VDD,
XOUT = 0 V
300
600
1500
ROSC2
VDD = 5.0 V; TA = 25; XTIN = VDD,
XTOUT = 0 V
1230
2630
4000
KΩ
S3C7324/P7324
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current(1)
Symbol
IDD1
IDD2
(2)
IDD3 (2)
Conditions
Main operating:
FC enable
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
Min
Typ
Max
Units
4.19 MHz
–
5.2
10
mA
Main operating:
6.0 MHz
–
3.5
8
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.19 MHz
2.5
5.5
VDD = 3 V ± 10%
6.0 MHz
1.6
4
4.19 MHz
1.2
3
1.0
2.5
Main idle mode(3):
6.0 MHz
PCON = 0111B, SCMOD =0000B
4.19 MHz
0.9
2.0
6.0 MHz
0.5
1.0
4.19 MHz
0.4
0.8
–
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
VDD = 3 V ± 10%
IDD4(2)
IDD5 (2)
IDD6(2)
IDD7(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
CPU = fxt/4, SCMOD = 1101B
VDD = 5 V ± 10%
–
15
30
–
6
15
–
0.5
3
Stop mode:
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
–
uA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. AMF or FMF is a normal input mode.
3. Data includes the power consumption for sub-system clock oscillation.
15-5
ELECTRICAL DATA
S3C7324/P7324
Table 15-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
Test Condition
Min
Typ
Max
Units
–
0.4
–
6.0
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
Oscillation frequency
–
0.4
–
6.0
MHz
VDD = 2.7 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 2.7 V
–
–
30
XIN input frequency (1)
–
0.4
–
6.0
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
VDD = 5 V
R = 15 KΩ, VDD = 5 V
R = 25 KΩ, VDD = 3 V
0.4
−
2.0
1.0
2.5
MHz
Oscillation frequency
(1)
C1
Crystal
Oscillator
Parameter
XIN
C2
XOUT
C1
(1)
C2
Stabilization time (2)
External
Clock
RC
Oscillator
XIN
XIN
XOUT
XOUT
R
Frequency (1)
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
15-6
S3C7324/P7324
ELECTRICAL DATA
Table 15-4. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XT IN
Parameter
Oscillation frequency
XT OUT
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 2.7 V
–
–
10
–
32
–
100
kHz
–
5
–
15
µs
(1)
C1
C2
Stabilization time (2)
External
Clock
Test Condition
XT IN XT OUT
XTIN input frequency
(1)
XTIN input high and
low level width (tXTL,
tXTH)
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
15-7
ELECTRICAL DATA
S3C7324/P7324
Table 15-5. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
f CLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O capacitance
Table 15-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
Interrupt input
tINTH, tINTL
high, low width
RESET Input Low
tRSL
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
INT0
(2)
INT1, INT2, INT4, KS0–KS2
10
Input
10
64
–
–
µs
–
–
µs
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting.
Table 15-6. A.C. Electrical Characteristics (continued)
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
8
8
8
bits
Absolute accuracy
–
–
–
–
±2
LSB
AD conversion
time
tCON
–
17
34/fxx (note)
–
µs
Analog input
voltage
VIAN
–
VSS
–
VDD
V
Analog input
impedance
RAN
–
2
1000
–
MΩ
NOTE: fxx stands for the system clock (fx or fxt).
15-8
S3C7324/P7324
ELECTRICAL DATA
Table 15-6. A.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input voltage
(peak to peak)
VIN
AMF/FMF mode, sine
wave input
0.3
–
VDD
V
Frequency
f AMF
AMF mode, sine wave
input; VIN = 300mVP-P
0.5
–
10
MHz
f FMF
FMF mode, sine wave
input; VIN = 300mVP-P
30
150
CPU CLOCK
Main OSC. Freq.
1.5 MHz
1.0475 MHz
6 MHz
4.19 MHz
3 MHz
750 kHz
500 kHz
250 kHz
400 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
When FC operates, operating voltage range is 3.0 V to 5.5 V.
Figure 15-1. Standard Operating Voltage Range
Table 15-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
VDDDR = 1.8 V
Min
Typ
Max
Unit
1.8
–
5.5
V
–
0.1
1
µA
15-9
ELECTRICAL DATA
S3C7324/P7324
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
t SREL
Figure 15-2. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
tSREL
t WAIT
Figure 15-3. Stop Mode Release Timing When Initiated by an Interrupt Request
15-10
S3C7324/P7324
ELECTRICAL DATA
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
0.8 VDD
0.2 VDD
Figure 15-4. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / fx
tXL
t XH
Xin
VDD – 0.1 V
0.1 V
Figure 15-5. Clock Timing Measurement at Xin
1 / fxt
t XTL
t XTH
XTin
VDD – 0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at XTin
15-11
ELECTRICAL DATA
S3C7324/P7324
tRSL
RESET
0.2 VDD
Figure 15-7. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4
KS0 to KS2
t INTH
0.8 VDD
0.2 VDD
Figure 15-8. Input Timing for External Interrupts and Quasi-Interrupts
15-12
S3C7324/P7324
MECHANICAL DATA
16
MECHANICAL DATA
OVERVIEW
The S3C7324 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 16-1.
23.90 ± 0.3
20.00 ± 0.2
0-8°
14.00 ± 0.2
64-QFP-1420F
+0.10
- 0.05
0.80 ± 0.20
0.10 MAX
#64
(1.00
)
17.90 ± 0.3
0.15
#1
0.05~0.25
+0.10
1.00
0.40 - 0.05
±
(1.00)
2.65 ± 0.10
0.15MAX
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 16-1. 64-QFP-1420F Package Dimensions
16-1
S3C7324/P7324
17
S3P7324 OTP
S3P7324 OTP
OVERVIEW
The S3P7324 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7324microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial
data format.
The S3P7324 is fully compatible with the S3C7324, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7324 is ideal for use as an evaluation chip for the S3C7324.
17-1
SEG7
SEG6
SEG5
SEG4
SEG8
52
53
54
55
SEG2
SEG3
56
57
SEG0
SEG1
59
58
COM2
COM3
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
S3P7324
21
22
23
24
25
26
27
28
29
30
31
32
P4.0
P4.1
P4.2
P4.3
P5.0
P5.2
P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
P5.1
20
(Top View)
P1.3/INT4
P2. 0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
SDAT/P3.2/ADC2
SCLK /P3.3/ADC3
V DD /V DD
V SS/V SS
XOUT
XIN
V PP/TEST
XTIN
XTOUT
RESET /RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
COM1
S3C7324/P7324
COM0
S3P7324 OTP
Figure 17-1. S3P7324 Pin Assignments (64-QFP)
17-2
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/ SEG20
P9.2/ SEG21
P9.1/SEG22
P9.0/ SEG23
P8.3/ SEG24
P8.2/ SEG25
P8.1/SEG26
P8.0/ SEG27
S3C7324/P7324
S3P7324 OTP
Table 17-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.2
SDAT
7
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input or push-pull output port.
P3.3
8
I/O
Serial clock pin. Input only pin.
TEST
SCLK
VPP (TEST)
13
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
RESET
RESET
16
I
Chip initialization
VDD / VSS
VDD / VSS
9/10
I
Logic power supply pin. VDD should be tied to +5
V during programming.
Table 17-2. Comparison of S3P7324 and S3C7324 Features
Characteristic
S3P7324
S3C7324
Program Memory
4K bytes EPROM
4K bytes mask ROM
Operating Voltage (VDD)
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
64 QFP
64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P7324, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
W
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
Mode
NOTE: "0" means low level; "1" means high level.
17-3
S3P7324 OTP
S3C7324/P7324
Table 17-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input high
voltage
Input low
voltage
Output high
voltage
17-4
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those
specified below
0.7 VDD
VIH2
P1, P3, RESET, P2.0−1 and
P6.1−3
0.8 VDD
VDD
VIH3
XIN, XOUT, XTIN, and XTOUT
VDD – 0.1
VDD
VIL1
All input pins except those
specified below
VIL2
P1, P3, RESET, P2.0−1 and
P6.1−3
0.2 VDD
VIL3
XIN, XOUT, XTIN, and XTOUT
0.1
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 1, 4, 5, and 6
VDD – 1.0
VOH2
VDD = 4.5 V to 5.5 V
IOH = –100 µA Port 8 and 9
VDD – 2.0
–
–
–
0.3 VDD
–
V
V
S3C7324/P7324
S3P7324 OTP
Table 17-4. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 1, 4, 5, and 6
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL = 100 µA ; Ports 8 and 9
–
–
1
Input high
leakage
current(note)
ILIH1
VIN = VDD
All input pins
–
–
3
Input low
leakage
current(note)
ILIL1
VIN = 0 V
All input pins
–
–
–3
Output high
leakage
current(note)
ILOH1
VOUT = VDD
All output pins
–
–
3
Output low
leakage
current (note)
ILOL
VOUT = 0 V
All output pins
–
–
–3
Pull-up
resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
20
40
80
VDD = 3 V
30
95
200
VIN = 0 V; VDD = 5 V
100
230
400
200
480
800
Output low
voltage
RL2
µA
KΩ
RESET
VDD = 3 V
NOTE:
Except for XIN, XOUT, XTIN, and XTOUT
17-5
S3P7324 OTP
S3C7324/P7324
Table 17-4. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
LCD voltage
dividing
resistor
RLCD
COM output
RCOM
RSEG
COM output
voltage
deviation
VDC
SEG output
voltage
deviation
VDS
17-6
VDD = 5 V
Typ
Max
Units
60
84
130
KΩ
−
3
6
5
15
VDD = 5 V
3
6
5
15
–
± 45
± 90
–
± 45
± 90
–
VDD = 3 V
impedance
Oscillator
feedback
resistor
TA = 25 øC
Min
VDD = 3 V
impedance
SEG output
Conditions
VDD = 5 V (VLC0-COMi)
mV
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (I = 0–27)
ROSC1
VDD = 5.0 V; TA = 25; XIN = VDD,
XOUT = 0 V
300
600
1500
ROSC2
VDD = 5.0 V; TA = 25; XTIN = VDD,
XTOUT = 0 V
1230
2630
4000
KΩ
S3C7324/P7324
S3P7324 OTP
Table 17-4. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current(1)
Symbol
IDD1
IDD2
(2)
IDD3 (2)
Conditions
Main operating:
FC enable
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
Min
Typ
Max
Units
4.19 MHz
–
5.2
10
mA
Main operating:
6.0 MHz
–
3.5
8
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
4.19 MHz
2.5
5.5
VDD = 3 V ± 10%
6.0 MHz
1.6
4
4.19 MHz
1.2
3
1.0
2.5
Main idle mode(3):
6.0 MHz
PCON = 0111B, SCMOD =0000B
4.19 MHz
0.9
2.0
6.0 MHz
0.5
1.0
4.19 MHz
0.4
0.8
–
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
VDD = 3 V ± 10%
IDD4(2)
IDD5 (2)
IDD6(2)
IDD7(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
CPU = fxt/4, SCMOD = 1101B
VDD = 5 V ± 10%
–
15
30
–
6
15
–
0.5
3
Stop mode:
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
–
uA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. AMF or FMF is a normal input mode.
3. Data includes the power consumption for sub-system clock oscillation.
17-7
S3P7324 OTP
S3C7324/P7324
Table 17-5. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
Test Condition
Min
Typ
Max
Units
–
0.4
–
6.0
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
Oscillation frequency
–
0.4
–
6.0
MHz
VDD = 2.7 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 2.7 V
–
–
30
XIN input frequency (1)
–
0.4
–
6.0
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
VDD = 5 V
R = 15 KΩ, VDD = 5 V
R = 25 KΩ, VDD = 3 V
0.4
−
2.0
1.0
2.5
MHz
Oscillation frequency
(1)
C1
Crystal
Oscillator
Parameter
XIN
C2
XOUT
C1
(1)
C2
Stabilization time (2)
External
Clock
RC
Oscillator
XIN
XIN
XOUT
XOUT
R
Frequency (1)
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
17-8
S3C7324/P7324
S3P7324 OTP
Table 17-6. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XT IN
Parameter
Oscillation frequency
XT OUT
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 2.7 V
–
–
10
–
32
–
100
kHz
–
5
–
15
µs
(1)
C1
C2
Stabilization time (2)
External
Clock
Test Condition
XT IN XT OUT
XTIN input frequency
(1)
XTIN input high and
low level width (tXTL,
tXTH)
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
17-9
S3P7324 OTP
S3C7324/P7324
Table 17-7. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
f CLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O capacitance
Table 17-8. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
Interrupt input
tINTH, tINTL
high, low width
RESET Input Low
tRSL
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.3
INT0
(2)
INT1, INT2, INT4, KS0–KS2
10
Input
10
64
–
–
µs
–
–
µs
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fxx as assigned by the IMOD0 register setting.
Table 17-8. A.C. Electrical Characteristics (continued)
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
8
8
8
bits
Absolute accuracy
–
–
–
–
±2
LSB
AD conversion
time
tCON
–
17
34/fxx (note)
–
µs
Analog input
voltage
VIAN
–
VSS
–
VDD
V
Analog input
impedance
RAN
–
2
1000
–
MΩ
NOTE: fxx stands for the system clock (fx or fxt).
17-10
S3C7324/P7324
S3P7324 OTP
Table 17-8. A.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input voltage
(peak to peak)
VIN
AMF/FMF mode, sine
wave input
0.3
–
VDD
V
Frequency
f AMF
AMF mode, sine wave
input; VIN = 300mVP-P
0.5
–
10
MHz
f FMF
FMF mode, sine wave
input; VIN = 300mVP-P
30
150
CPU CLOCK
Main OSC. Freq.
1.5 MHz
1.0475 MHz
6 MHz
4.19 MHz
3 MHz
750 kHz
500 kHz
250 kHz
400 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
When FC operates, operating voltage range is 3.0 V to 5.5 V.
Figure 17-2. Standard Operating Voltage Range
Table 17-9. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
VDDDR = 1.8 V
Min
Typ
Max
Unit
1.8
–
5.5
V
–
0.1
1
µA
17-11
S3P7324 OTP
S3C7324/P7324
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
t SREL
Figure 17-3. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
tSREL
t WAIT
Figure 17-4. Stop Mode Release Timing When Initiated by an Interrupt Request
17-12
S3C7324/P7324
S3P7324 OTP
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
0.8 VDD
0.2 VDD
Figure 17-5. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / fx
tXL
t XH
Xin
VDD – 0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at Xin
1 / fxt
t XTL
t XTH
XTin
VDD – 0.1 V
0.1 V
Figure 17-7. Clock Timing Measurement at XTin
17-13
S3P7324 OTP
S3C7324/P7324
tRSL
RESET
0.2 VDD
Figure 17-8. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4
KS0 to KS2
t INTH
0.8 VDD
0.2 VDD
Figure 17-9. Input Timing for External Interrupts and Quasi-Interrupts
17-14