RENESAS TBB1010

TBB1010
Twin Build in Biasing Circuit MOS FET IC
VHF/VHF RF Amplifier
ADE-208-1607B (Z)
3rd. Edition
Feb. 2003
Features
•
•
•
•
•
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
High |yfs|=29mS ×2
Suitable for World Standard Tuner RF amplifier.
Very useful for total tuner cost reduction.
Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200 V at C = 200 pF,
Rs = 0 conditions.
• Provide mini mold packages; CMPAK-6
Outline
CMPAK-6
6
5
4
2
1
Notes:
1.
2.
3
1. Drain(1)
2. Source
3. Drain(2)
4. Gate-1(2)
5. Gate-2
6. Gate-1(1)
Marking is “KM”.
TBB1010 is individual type number of HITACHI TWIN BBFET.
TBB1010
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
VDS
6
V
Gate1 to source voltage
VG1S
+6
-0
V
Gate2 to source voltage
VG2S
+6
-0
V
Drain current
ID
30
mA
*3
Channel power dissipation
Pch
250
mW
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Notes: 3. Value on the glass epoxy board (50mm × 40mm × 1mm).
Rev.2, Feb. 2003, page 2 of 10
TBB1010
Electrical Characteristics
(Ta = 25°C)
The below specification are applicable for FET1 and FET2 unit
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS
—
—
V
ID = 200 µA, VG1S = VG2S = 0
Gate1 to source breakdown
voltage
V(BR)G1SS +6
—
—
V
IG1 = +10 µA, VG2S = VDS = 0
Gate2 to source breakdown
voltage
V(BR)G2SS +6
—
—
V
IG2 = +10 µA, VG1S = VDS = 0
Gate1 to source cutoff current
IG1SS
—
—
+100
nA
VG1S = +5 V, VG2S = VDS = 0
Gate2 to source cutoff current
IG2SS
—
—
+100
nA
VG2S = +5 V, VG1S = VDS = 0
Gate1 to source cutoff voltage
VG1S(off)
0.6
—
1.1
V
VDS = 5 V, VG2S = 4 V,
ID = 100 µA
Gate2 to source cutoff voltage
VG2S(off)
0.6
—
1.1
V
VDS = 5 V, VG1S = 5 V,
ID = 100 µA
Drain current
ID(op)
12
16
20
mA
VDS = 5 V, VG1 = 5 V
VG2S = 4 V, RG = 120 kΩ
Forward transfer admittance
|yfs|
24
29
—
mS
VDS = 5 V, VG1 = 5 V, VG2S =4V
RG = 120 kΩ, f = 1 kHz
Input capacitance
Ciss
1.7
2.1
2.5
pF
VDS = 5 V, VG1 = 5 V
Output capacitance
Coss
1.0
1.4
1.8
pF
VG2S =4 V, RG = 120 kΩ
Reverse transfer capacitance
Crss
—
0.03
0.05
pF
f = 1 MHz
Power gain
PG
25
30
—
dB
VDS = VG1 = 5 V, VG2S = 4 V
Noise figure
NF
—
1.1
1.8
dB
RG = 120 kΩ, f = 200 MHz
6
Rev.2, Feb. 2003, page 3 of 10
TBB1010
Test Circuits
• DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG)
Measurment of FET1
RG
Gate 1
Gate 2
Open
VG2
VG1
ID
VD
A
Drain
Open
Source
Measurment of FET2
Gate 2
VG2
Gate 1
RG
Open
VG1
A
Open
Drain
Source
Rev.2, Feb. 2003, page 4 of 10
ID
VD
TBB1010
• Equivalent Circuit
No.1
No.6
Drain(1)
Gate-1(1)
No.2
No.5
BBFET-(1)
Source
Gate-2
BBFET-(2)
No.3
No.4
Drain(2)
Gate-1(2)
• 200 MHz Power Gain, Noise Figure Test Circuit
1000p
47k
Input (50 Ω)
VT
VG2
VT
1000p
1000p
47k
1000p
47k
TWINBBFET
1000p
L2
L1
10p max
1000p
1000p
36p
Output (50 Ω)
1SV70
RG
RFC
120k
1SV70
1000p
V D = V G1
Unit : Resistance (Ω)
Capacitance (F)
L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns
L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns
RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns
Rev.2, Feb. 2003, page 5 of 10
Typical Output Characteristics
25
200
100
0
50
100
150
Ambient Temperature
20
15
0
15
10
kΩ
0k
Ω
18
5
0
200
R
G=
10
82
0
0
kΩ
k
kΩ
Ω
300
V G2S = 4 V
V G1 = VDS
12
I D (mA)
400
Maximum Channel Power
Dissipation Curve
Drain Current
Channel Power Dissipation
Pch* (mW)
TBB1010
Ta (°C)
1
2
3
Drain to Source Voltage
4
5
V DS (V)
* Value on the glass epoxy board (50mm × 40mm × 1mm)
20
Forward Transfer Admittance |y fs | (mS)
Drain Current
I D (mA)
25
Drain Current vs. Gate1 Voltage
V DS = 5 V
R G = 120 kΩ
4V
15
3V
10
2V
5
VG2S = 1 V
0
1
2
Gate1 Voltage
Rev.2, Feb. 2003, page 6 of 10
3
V G1
4
(V)
5
50
Forward Transfer Admittance
vs. Gate1 Voltage
V DS = 5 V
R G = 120 kΩ
40 f = 1 kHz
30
4V
3V
20
2V
10
VG2S = 1 V
0
1
2
Gate1 Voltage
3
4
V G1 (V)
5
TBB1010
Input Capacitance vs.
Gate2 to Source Voltage
Drain Current vs. Gate Resistance
4
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
25
20
15
10
5
0
10
20
50
100 200
Input Capacitance Ciss (pF)
Drain Current I D (mA)
30
3
2
0
500 1000
V DS = 5 V
V G1 = 5 V
R G = 120 kΩ
f = 1 MHz
1
Gate Resistance R G (kΩ)
0
30
25
20
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
f = 200 MHz
20
50 100 200
500 1000
Gate Resistance R G (kΩ)
Noise Figure NF (dB)
4
35
Power Gain PG (dB)
4
Noise Figure vs. Gate Resistance
Power Gain vs. Gate Resistance
10
10
3
Gate2 to Source Voltage V G2S (V)
40
15
2
1
V DS = 5 V
V G1 = 5 V
V G2S = 4 V
f = 200 MHz
3
2
1
0
10
20
50
100
200
500 1000
Gate Resistance R G (kΩ)
Rev.2, Feb. 2003, page 7 of 10
TBB1010
Gain Reduction vs.
Gate2 to Source Voltage
Gain Reduction GR (dB)
50
V DS = V G1 = 5 V
R G = 120 kΩ
40
30
20
10
0
0
1
2
3
Gate2 to Source Voltage V G2S (V)
Rev.2, Feb. 2003, page 8 of 10
4
TBB1010
Package Dimensions
As of July, 2002
(0.65)
+ 0.1
0.15 – 0.05
0 – 0.1
0.9 ± 0.1
+ 0.1
– 0.05
(0.2)
6-0.2
(0.65)
2.1 ± 0.3
2.0 ± 0.2
1.3 ± 0.2
(0.425) 1.25 ± 0.1 (0.425)
Unit: mm
Hitachi Code
JEDEC
JEITA
Mass (reference value)
CMPAK-6
—
Conforms
0.006 g
Rev.2, Feb. 2003, page 9 of 10
TBB1010
Disclaimer
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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
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products.
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Copyright © Hitachi, Ltd., 2003. All rights reserved. Printed in Japan.
Colophon 7.0
Rev.2, Feb. 2003, page 10 of 10