Cypress Semiconductor Product Qualification Report QTP# 002902 VERSION 1.1 May, 2003 Phase-Aligned System Clock, 3.3V L28 Technology, Fab 2 CY2300 CY2303 10-MHz to 166.67-MHZ CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Reliability Director (408) 432–7069 Rene Rodgers Staff Reliability Engineer (408) 943–2732 Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 2 of 10 May, 2003 PRODUCT QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 95197 New L28 Technology Qualification Feb 96 95501 New CY2907 Product Qualification May 97 002902 New CY2300 Product Qualification Sep 00 Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 3 of 10 May, 2003 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify CY2300 device in qualified L28 Technology, Fab 2 Marketing Part #: CY2300 and CY2303 Device Description: 3.3V, Commercial and Industrial available in 8-lead SOIC package Cypress Division: Cypress Semiconductor Corporation - Clock Product Division, WA Division Overall Die (or Mask) REV Level (pre-requisite for qualification): What ID markings on Die: Rev. A 7C80730A TECHNOLOGY/FAB PROCESS DESCRIPTION - L28-CTI Number of Metal Layers: 2 Metal Composition: Metal 1: 500ATi/1,200A TiW/6.000A Al/1,200A TiW Metal 2: 1,500A TiW/10,000A Al/150A Ti Passivation Type and Materials: 3,000A TEOS + 15.000A Si2N4 Generic Process Technology/Design Rule (µ-drawn): CMOS, Single Poly, Double Metal /0.65 µm Gate Oxide Material/Thickness (MOS): SiO2 / 145 A Name/Location of Die Fab (prime) Facility: Cypress Semiconductor – Round Rock, TX Die Fab Line ID/Wafer Process ID: Fab2/L28 PACKAGE TYPE 8-lead SOIC ASSEMBLY FACILITY SITE PHIL-OP, PHIL-M Note: Package Qualification details upon request Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 4 of 10 May, 2003 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: S0815H 8-lead SOIC Sumitomo EME6300H Mold Compound Flammability Rating: V-O per UL94 Oxygen Rating Index: >28% Lead Frame Designation: S Lead Frame Material: Copper Alloy C19400 Full Hard Lead Finish, Composition / Thickness: 85%Sn- 15%Pb Die Backside Preparation Method/Metallization: N/A Die Separation Method: Wafer Saw Die Attach Supplier: Ablebond Die Attach Material: 84-1 Bond Diagram Designation 10-03830 Wire Bond Method: Thermosonic Wire Material/Size: Gold, 1.0mil Thermal Resistance Theta JA °C/W: 98.4 Package Cross Section Yes/No: N/A Assembly Process Flow: 49-65002M Name/Location of Assembly (prime) facility: OSE Philippines ELECTRICAL TEST / FINISH DESCRIPTION Test Location: OSE (PHIL-OP) Fault Coverage: 100% Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 5 of 10 May, 2003 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS Stress/Test Test Condition (Temp/Bias) Result P/F High Temperature Operating Life Early Failure Rate Dynamic Operating Condition, Vcc = 5.75/5.5V, 150C P High Temperature Operating Life Latent Failure Rate Dynamic Operating Condition, Vcc = 5.50V, 150°C P High Temperature Steady State Life Static Operating Condition, Vcc = 5.5V, 150°C P High Accelerated Saturation Test (HAST) 140°C, 85%RH, 5.5V Precondition: JESD22 Moisture Sensitivity Level 1 P 168 Hrs., 85°C/85%RH+3IR-Reflow, 220°C+5, -0°C Temperature Cycle (Plastic device) MIL-STD-883C, Method 1010, Condition C, -65°C to 150°C Precondition: JESD22 Moisture Sensitivity Level 1 168 Hrs., 85°C/85%RH+3IR-Reflow, 220°C+5, -0°C P Pressure Cooker 121°C, 100%RH Precondition: JESD22 Moisture Sensitivity Level 1 P 168 Hrs., 85°C/85%RH+3IR-Reflow, 220°C+5, -0°C Cold Life Test -30°C, 6.5V P Long Life Verification Dynamic Operating Condition, Vcc = 5.50V, 150°C (95197) P SEM Analysis MIL-STD-883, Method 2018 P Age Bond Strength MIL-STD-883, Method 2011 P High Temperature Storage Plastic 165, no bias P Electrostatic Discharge Human Body Model (ESD-HBM) 2200V MIL-STD-883, Method 3015.7 P Electrostatic Discharge Charge Device Model (ESD-CDM) 500V Cypress Spec. 25-00020 P Latchup Sensitivity +/-300mA In accordance with JEDEC 17. Cypress Spec. 01-00081 P Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 6 of 10 May, 2003 RELIABILITY FAILURE RATE SUMMARY Stress/Test High Temperature Operating Life Early Failure Rate High Temperature Operating Life1,2 Long Term Failure Rate 1 2 3 Device Tested/ Device Hours # Fails Activation Energy Thermal3 A.F Failure Rate4 2065 0 N/A N/A 0 PPM 341,508 DHRs 0 0.7 170 16 FIT Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. 4 EFR and LFR are based on QTP 95197 and QTP 95501 Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 7 of 10 May, 2003 RELIABILITY TEST DATA QTP#: 951971 DEVICE ASSY-LOC FABLOT# ASSYLOT# DURATION ==================== ======== ======== ============== ======== STRESS: HIGH TEMPERATURE STORAGE-PLASTIC (165C, NO BIAS) CY2291SC CY2291SC PHIL-M PHIL-M 3519671 3519671 13040(SWR) 13040(SWR) 168 552 S/S ==== REJ === 76 78 0 0 FAIL MODE ================================ CY2291SC PHIL-M 3520751 13109(SWR) 168 80 0 CY2291SC PHIL-M 3520751 13109(SWR) 552 80 0 ---------------------------------------------------------------------------------------------------------------STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 5.50V) CY2291SC PHIL-M CY2291SC PHIL- M 3519671 3518546 13040(SWR) 13041(SWR) 48 354 0 48 354 0 CY2291SC PHIL-M 3520751 13109(SWR) 48 354 0 ---------------------------------------------------------------------------------------------------------------STRESS: HI-ACCEL SATURATION TEST (140C, 85%RH, 5.5V), PRECONDITION 48 HRS PCT CY2291SC PHIL -M 3518546 13041(SWR) 128 49 0 CY2291SC PHIL-M 3520751 13109(SWR) 128 50 0 ---------------------------------------------------------------------------------------------------------------STRESS: HIGH TEMP STEADY STATE LIFE TEST (150C, 5.5V) CY2291SC CY2291SC PHIL-M PHIL-M 3519671 3519671 13040(SWR) 13040(SWR) 80 168 76 76 0 0 CY2291SC CY2291SC PHIL-M PHIL-M 3518546 3518546 13041(SWR) 13041(SWR) 80 168 76 76 0 0 CY2291SC PHIL-M 3520751 13109(SWR) 80 76 0 CY2291SC PHIL-M 3520751 13109(SWR) 168 76 0 ---------------------------------------------------------------------------------------------------------------STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 5.5V) CY2291SC CY2291SC PHIL-M PHIL-M 3519671 3519671 13040(SWR) 13040(SWR) 80 500 116 116 0 0 CY2291SC CY2291SC CY2291SC PHIL-M PHIL-M PHIL-M 3518546 3518546 3518546 13041(SWR) 13041(SWR) 13041(SWR) 80 197 500 120 120 116 0 0 0 CY2291SC PHIL-M 3520751 13109(SWR) 80 116 0 CY2291SC PHIL-M 3520751 13109(SWR) 500 116 0 ---------------------------------------------------------------------------------------------------------------STRESS: EXTENDED DYNAMIC BURN-IN (150C, 5.5V) CY2291SC PHIL-M 3518546 13041(SWR) 1000 116 0 CY2291SC PHIL-M 3518546 13041(SWR) 2000 116 0 ---------------------------------------------------------------------------------------------------------------STRESS: COLD LIFE TEST (-30C, 6.5V) CY2291SC CY2291SC 1 PHIL-M PHIL-M L28 technology qualification. 3519671 3519671 13040(SWR) 13040(SWR) 500 1000 47 47 0 0 Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 8 of 10 May, 2003 RELIABILITY TEST DATA QTP#: DEVICE ==================== STRESS: CY2291SC ASSY-LOC ======== FABLOT# ======== ASSYLOT# ============== 95197 DURATION ======== S/S ==== REJ === 45 0 FAIL MODE ================================ PRESSURE COOKER TEST (121C, 100%RH) PHIL -M 3518546 13041(SWR) 168 CY2291SC PHIL-M 3520751 13109(SWR) 168 50 0 ---------------------------------------------------------------------------------------------------------------STRESS: TEMP CYCLE, COND. C, -65 TO 150C, PRECONDITION 48 HRS PCT CY2291SC CY2291SC PHIL-M PHIL-M CY2291SC CY2291SC PHIL- M PHIL- M 3519671 3519671 3518546 3518546 13040(SWR) 13040(SWR) 13041(SWR) 13041(SWR) 300 1000 300 1000 46 46 0 0 49 49 0 0 CY2291SC PHIL-M 3520751 13109(SWR) 300 50 0 CY2291SC PHIL-M 3520751 13109(SWR) 1000 50 0 ---------------------------------------------------------------------------------------------------------------- Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 9 of 10 May, 2003 RELIABILITY TEST DATA QTP#: 955012 DEVICE ASSY-LOC FABLOT# ASSYLOT# DURATION ==================== ======== ======== ============== ======== STRESS: HIGH TEMPERATURE STORAGE-PLASTIC (165C, NO BIAS) S/S ==== REJ === FAIL MODE ================================ CY2907-SC PHIL-M 3601147 3601147 168 76 0 CY2907-SC PHIL-M 3601147 3601147 552 76 0 --------------------------------------------------------------------------------------------------------------STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE (150C, 5.50V) CY2907-SC PHIL-M 3601147 3601147 48 1003 0 --------------------------------------------------------------------------------------------------------------STRESS: HI-ACCEL SATURATION TEST (140C,85%RH, 5.5V), PRECOND. 168 HRS 85C/85%RH CY2907-SC PHIL-M 3601147 3601147 128 48 0 --------------------------------------------------------------------------------------------------------------STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE (150C, 5.50V) CY2907-SC PHIL-M 3601147 3601147 500 120 0 --------------------------------------------------------------------------------------------------------------STRESS: TC COND. C, -65 TO 150C, PRECOND. 168 HRS 85C/85%RH CY2907-SC PHIL-M 3601147 3601147 300 48 0 CY2907-SC PHIL-M 3601147 3601147 1000 48 0 --------------------------------------------------------------------------------------------------------------- 2 7C80700 die qualification which QTP 96303 was based on with 4 layer mask changed implementation. Cypress Semiconductor 3.3V Phase-Aligned System Clock, L28 Technology, Fab 2 Device: CY2300 QTP# 002902, V. 1.1 Page 10 of 10 May, 2003 Reliability Test Data QTP #: Device Fab Lot # 002902 Assy Lot # Assy Loc Duration Samp Rej 610033265 PHIL-OP 500V 9 0 610033265 PHIL-OP 2200V 9 0 COMP 3 STRESS: ESD-CDM (500V) CY2300SC 2026276 STRESS: ESD-HBM (2,200V) CY2300SC 2026276 STRESS: STATIC LATCH-UP TESTING (125C, 10V, +/-300mA) CY2300SC 2026276 610033265 PHIL-OP 0 Failure Mechanism