RF1K49224
Data Sheet
August 1999
File Number
3.5A/2.5A, 30V, 0.060/0.150 Ohms,
Complementary LittleFET™ Power
MOSFET
Features
The RF1K49224 complementary power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
intergrated circuits.
• rDS(ON) = 0.060Ω (N-Channel)
rDS(ON) = 0.150Ω (P-Channel)
• 3.5A, 30V (N-Channel)
2.5A, 30V (P-Channel)
• Temperature Compensating PSPICE® Model
• Thermal Impedance PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49224.
Ordering Information
PART NUMBER
RF1K49224
PACKAGE
MS-012AA
4330.1
Symbol
BRAND
D1(8)
D1(7)
RF1K49224
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e. RF1K4922496.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
9-16
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RF1K49224
TA = 25oC Unless Otherwise Specified
N-CHANNEL
30
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS= 20kΩ ) . . . . . . . . . . . . . . .VDGR
30
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
Drain Current
Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . ID
3.5
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Refer to Peak Current Curve
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
2
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.016
Operating and Storage Temperature . . . . . . . . . . . . TJ, TSTG
-55 to 150
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . TL
300
Package Body for 10s, See Techbrief 334 . . . . . . . . . .Tpkg
260
Absolute Maximum Ratings
P-CHANNEL
-30
-30
±20
UNITS
V
V
V
2.5
Refer to Peak Current Curve
Refer to UIS Curve
2
0.016
-55 to 150
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
N-Channel Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
30
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
1
-
3
V
-
-
1
µA
-
-
50
µA
-
-
100
nA
-
-
0.060
Ω
0.132
Ω
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
IDSS
IGSS
rDS(ON)
VDS = 30V,
VGS = 0V
TA = 25o C
TA = 150o C
VGS = ±20V
ID = 3.5A
VGS = 10V
VGS = 4.5V
Turn-On Time
tON
Turn-On Delay Time
-
-
50
ns
-
10
-
ns
tr
-
30
-
ns
td(OFF)
-
60
-
ns
tf
-
45
-
ns
tOFF
-
-
130
ns
-
35
45
nC
-
13
17
nC
-
2.3
2.9
nC
-
575
-
pF
-
275
-
pF
-
100
-
pF
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
VDD = 15V, ID ≅ 3.5A,
RL = 4.29Ω, VGS = 10V,
RGS = 25Ω
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDD = 24V,
ID ≅ 3.5A,
RL = 6.86Ω
Ig(REF) = 1.0mA
VDS = 25V, VGS = 0V,
f = 1MHz
-
-
62.5
oC/W
MIN
TYP
MAX
UNITS
ISD = 3.5A
-
-
1.25
V
ISD = 3.5A, dISD/dt = 100A/µs
-
-
45
ns
Pulse width = 1s
Device mounted on FR-4 material
N-Channel Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
VSD
trr
9-17
TEST CONDITIONS
RF1K49224
P-Channel Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
-30
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
IDSS
IGSS
rDS(ON)
VDS = -30V,
VGS = 0V
-1
-
-3
V
TA = 25o C
-
-
-1
µA
TA = 150o C
-
-
-50
µA
-
-
100
nA
-
-
0.150
Ω
0.360
Ω
VGS = ±20V
ID = 2.5A
VGS = -10V
VGS = -4.5v
Turn-On Time
tON
Turn-On Delay Time
-
-
40
ns
-
9
-
ns
tr
-
19
-
ns
td(OFF)
-
60
-
ns
tf
-
34
-
ns
tOFF
-
-
140
ns
-
28
35
nC
-
15
19
nC
-
1.5
1.9
nC
-
580
-
pF
-
260
-
pF
-
38
-
pF
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = -15V, ID ≅ 2.5A,
RL = 6Ω, VGS = -10V,
RGS = 25Ω
Total Gate Charge
Qg(TOT)
VGS = 0V to -20V
Gate Charge at -10V
Qg(-10)
VGS = 0V to -10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDD = -24V,
ID ≅ 2.5A,
RL = 9.6Ω
Ig(REF) = -1.0mA
VDS = -25V, VGS = 0V,
f = 1MHz
-
-
62.5
oC/W
MIN
TYP
MAX
UNITS
ISD = -2.5A
-
-
-1.25
V
ISD = -2.5A, dISD/dt = -100A/µs
-
-
49
ns
Pulse width = 1s
Device mounted on FR-4 material
P-Channel Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
Typical Performance Curves (N-Channel)
4.0
3.5
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
3.0
2.5
2.0
1.5
1.0
0.2
0.5
0
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
9-18
25
75
100
125
50
TA, AMBIENT TEMPERATURE (oC)
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
RF1K49224
Typical Performance Curves (N-Channel)
(Continued)
ZθJA, NORMALIZED
THERMAL IMPEDANCE
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-1
100
10-2
t, RECTANGULAR PULSE DURATION (s)
101
102
103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
10
5ms
10ms
1
100ms
0.1
200
TJ = MAX RATED
TA = 25oC
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1s
VDSS(MAX) = 30V
0.01
0.1
1
TA = 25oC
100
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
DC
10
1
10-5
100
10-4
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
10-1
100
100
VGS = 5V
VGS = 20V
VGS = 10V
20
VGS = 4.5V
15
VGS = 4V
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
5
0
0
1
2
3
VGS = 3V
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
9-19
101
25
STARTING TJ = 150oC
NOTE:
10-2
FIGURE 5. PEAK CURRENT CAPABILITY
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
1
10
tAV, TIME IN AVALANCHE (ms)
10-3
t, PULSE WIDTH (s)
STARTING TJ = 25oC
1
0.1
150 - TA
125
= I25
10
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
10
I
VGS = 10V
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
FIGURE 7. SATURATION CHARACTERISTICS
5
RF1K49224
Typical Performance Curves (N-Channel)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
250
20
-55oC
150oC
15
10
5
150
100
ID = 0.5A
50
0
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 7.0A
ID = 3.5A
ID = 1.75A
200
0
0
7.5
3
4
5
6
7
8
9
10
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
2.0
VGS = VDS, ID = 250µA
NORMALIZED GATE
1.0
0.5
0
-80
-40
0
40
80
120
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 3.5A
1.5
1.5
1.0
0.5
0
-80
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1000
2.0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
ID = 250µA
1.5
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VDD = 15V
25oC
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID(ON), ON-STATE DRAIN CURRENT (A)
25
(Continued)
1.0
0.5
750
CISS
500
COSS
250
CRSS
0
-80
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
9-20
0
0
5
10
15
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
RF1K49224
(Continued)
30
10.0
VDD = BVDSS
VDD = BVDSS
22.5
7.5
RL = 8.57Ω
Ig(REF) = 0.75mA
VGS = 10V
15
5.0
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
7.5
2.5
0
0
I g ( REF )
20 -----------------------I g ( ACT )
t, TIME (ms)
VGS , GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
Typical Performance Curves (N-Channel)
I g ( REF )
80 -----------------------I g ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms (N-Channel)
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
VDS
VGS
+
-
VDD
10%
10%
0
DUT
RGS
VGS
90%
VGS
0
FIGURE 17. SWITCHING TIME TEST CIRCUIT
9-21
10%
50%
50%
PULSE WIDTH
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
RF1K49224
Test Circuits and Waveforms (N-Channel)
VDS
(Continued)
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
-
VGS = 2V
DUT
0
Ig(REF)
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORM
1.2
-3.0
1.0
-2.5
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves (P-Channel)
0.8
0.6
0.4
0.2
-2.0
-1.5
-1.0
-0.5
0
0
0
25
50
75
100
125
TA , AMBIENT TEMPERATURE (oC)
150
FIGURE 21. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
25
75
100
125
50
TA, AMBIENT TEMPERATURE (oC)
150
FIGURE 22. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
THERMAL IMPEDANCE
ZθJA, NORMALIZED
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-1
100
10-2
t, RECTANGULAR PULSE DURATION (s)
101
FIGURE 23. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
9-22
102
103
RF1K49224
Typical Performance Curves (P-Channel)
-100
TJ = MAX RATED
TA = 25oC
-10
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
-50
(Continued)
5ms
10ms
-1
100ms
-0.1
1s
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-0.01
-0.1
VDSS(MAX) = -30V
-1
VGS = -20V TA = 25oC FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
DC
-10
-1
10-5
-100
10-4
10-3
10-1
100
101
FIGURE 25. PEAK CURRENT CAPABILITY
-20
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
VGS = -20V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
VGS = -7V
STARTING TJ = 150oC
ID, DRAIN CURRENT (A)
VGS = -10V
STARTING TJ = 25oC
-16
VGS = -8V
VGS = -6V
-12
VGS = -5V
-8
VGS = -4.5V
-4
0
1
10
tAV, TIME IN AVALANCHE (ms)
10-2
t, PULSE WIDTH (s)
-15
IAS, AVALANCHE CURRENT (A)
150 - TA
125
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FIGURE 24. FORWARD BIAS SAFE OPERATING AREA
-1
0.1
= I25
-10
VDS, DRAIN TO SOURCE VOLTAGE (V)
-10
I
VGS = -10V
100
0
-1.5
-3.0
-4.5
-6.0
-7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 26. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
-16
500
150oC
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID(ON), ON-STATE DRAIN CURRENT (A)
-20
-55oC
25oC
-12
-8
-4
0
0
-2
-4
-6
-8
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 28. TRANSFER CHARACTERISTICS
9-23
FIGURE 27. SATURATION CHARACTERISTICS
-10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
400
ID = -5.0A
ID = -2.5A
300
ID = -1.25A
200
ID = -0.625A
100
0
-2
-4
-6
-8
-10
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 29. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
RF1K49224
Typical Performance Curves (P-Channel)
(Continued)
1.2
1.5
1.0
0.5
-40
0
40
80
120
1.0
0.8
0.6
0.4
-80
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 30. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
750
1.2
ID = -250µA
C, CAPACITANCE (pF)
CISS
1.1
1.0
0.9
0.8
-80
160
FIGURE 31. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
600
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
450
COSS
300
150
CRSS
0
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE (oC)
0
160
VDS , DRAIN TO SOURCE VOLTAGE (V)
-10.0
VDD = BVDSS
VDD = BVDSS
-22.5
0
-15
-7.5
RL = 12Ω
Ig(REF) = -0.26mA
VGS = -10V
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
I g ( REF )
20 -----------------------I g ( ACT )
t, TIME (µs)
-5.0
-2.5
0
I g ( REF )
80 --------------------I g ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 34. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
9-24
-20
-25
FIGURE 33. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-30.0
-7.5
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 32. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
-15.0
-5
VGS , GATE TO SOURCE VOLTAGE (V)
0
-80
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = -250µA
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V, ID = -2.5A
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.0
RF1K49224
Test Circuits and Waveforms (P-Channel)
VDS
tAV
L
0
VARY tP TO OBTAIN
REQUIRED PEAK IAS
-
RG
+
VDD
DUT
0V
VDD
tP
VGS
IAS
IAS
VDS
tP
0.01Ω
BVDSS
FIGURE 35. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 36. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
tr
0
RL
tf
10%
10%
VDS
VGS
-
VDS
VDD
+
VGS
90%
90%
VGS
0
10%
DUT
RGS
50%
50%
PULSE WIDTH
90%
FIGURE 37. SWITCHING TIME TEST CIRCUIT
FIGURE 38. RESISTIVE SWITCHING WAVEFORMS
VDS
RL
VDS
Qg(TH)
0
VGS= -2V
VGS
-
Qg(-10)
+
DUT
VGS= -10V
-VGS
VDD
VGS= -20V
VDD
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 39. GATE CHARGE TEST CIRCUIT
9-25
FIGURE 40. GATE CHARGE WAVEFORMS
RF1K49224
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which
the devices are subjected.
1. Always preheat the device.
2. The delta temperature between the preheat and soldering
should always be less than 100oC. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
9-26
3. The maximum temperature gradient should be less than 5oC
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be
at least 30oC higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
exceed 260oC for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.
RF1K49224
PSPICE Electrical Model (N-Channel)
SUBCKT RF1K49224 2 1 3 ;
N-Channel Model rev 12/15/94
CA 12 8 1.75e-9
CB 15 14 1.80e-9
CIN 6 8 1.20e-9
DPLCAP
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
5
10
LDRAIN
DBREAK
EBREAK 11 7 17 18 33.29
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
RDRAIN
ESG
+
11
6
8
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 1.233e-9
LSOURCE 3 7 0.452e-9
EBREAK
16
VTO +
IT 8 17 1
EVTO
9
20 + 18
8
LGATE RGATE
21
6
8
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
MOS2
RSOURCE
7
LSOURCE
3
SOURCE
S2A
S1A
12
DBODY
CIN
RIN
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1e-4
RGATE 9 20 1.83
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 13.5e-3
RVTO 18 19 RVTOMOD 1
+
17
18
MOS1
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
S1A
S1B
S2A
S2B
DRAIN
2
13
8
S1B
RBREAK
15
14
13
17
18
S2B
RVTO
13
CB
CA
+
EGS
6
8
EDS
+ 14
5
8
IT
19
VBAT
+
VBAT 8 19 DC 1
VTO 21 6 0.1
.MODEL DBDMOD D (IS = 2.50e-13 RS = 1.35e-2 TRS1 = 4.31e-5 TRS2 = 2.15e-5 CJO = 9.33e-10 TT = 2.08e-8)
.MODEL DBKMOD D (RS = 1.14 TRS1 = 2.23e-3 TRS2 = -8.91e-6)
.MODEL DPLCAPMOD D (CJO = 7.99e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.15 KP = 6.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 7.74e-4 TC2 = 1.13e-6)
.MODEL RDSMOD RES (TC1 = 4.5e-3 TC2 = -7.45e-7)
.MODEL RVTOMOD RES (TC1 = -4.16e-3 TC2 = 2.16e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.15 VOFF= -5.15)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.15 VOFF= -7.15)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.6 VOFF= 2.4)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.4 VOFF= -2.6)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
9-27
RF1K49224
PSPICE Electrical Model (P-Channel)
SUBCKT RF1K49224 2 1 3 ;
P-Channel Model rev 4/7/97
CA 12 8 7.29e-10
CB 15 14 5.01e-10
CIN 6 8 5.55e-10
LDRAIN
ESG
10
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
+
5
51
EBREAK 5 11 17 18 -35.46
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EBREAK
ESLC
+
17
18
-
-
50
DPLCAP
LGATE
RDRAIN
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 1.27e-9
LSOURCE 3 7 4.20e-10
9
-
20
21
18 +
22
MWEAK
11
MMED
DBREAK
MSTRO
LSOURCE
CIN
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 19.3e-3
RGATE 9 20 7.44
RLDRAIN 2 5 10
RLGATE 1 9 12.7
RLSOURCE 3 7 4.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 65.37e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
DBODY
16
6
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
RSLC2
IT 8 17 1
DRAIN
2
5
+
8
6
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
14
+
+
6
8
EGS
19
EDS
-
-
IT
VBAT
5
8
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*48),2.5))}
.MODEL DBODYMOD D (IS = 3.30e-13 RS = 4.56e-2 TRS1 =6.98e-4 TRS2 =8.08e-7 CJO = 8.21e-10 TT = 3.51e-8 M=0.4)
.MODEL DBREAKMOD D (RS = 8.18e-1 TRS1 =5.28e-3 TRS2 = -7.18e-5
.MODEL DPLCAPMOD D (CJO = 2.52e-10 IS = 1e-30 N = 10 M=0.6)
.MODEL MMEDMOD PMOS (VTO= -1.95 KP=0.75 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=7.44)
.MODEL MSTROMOD PMOS (VTO= -2.44 KP= 7.25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD PMOS (VTO= -1.68 KP=0.045 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=74.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 9.45e-4 TC2 = -1.01e-7)
.MODEL RDRAINMOD RES (TC1 = 3.69e-3 TC2 = 5.90e-6)
.MODEL RSLCMOD RES (TC1=3.46e-3 TC2= 1.26e-6)
.MODEL RSOURCEMOD RES (TC1=3.69e-3 TC2=5.90e-6)
.MODEL RVTHRESMOD RES (TC=-5.19e-4 TC2= 5.02e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.54e-3 TC2 = -6.53e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 6.94 VOFF= 3.94)
VON = 3.94 VOFF= 6.94)
VON = 0.40 VOFF= -2.60)
VON = -2.60 VOFF= 0.40)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9-28
RF1K49224
PSpice Thermal Model
REV 28 Feb 97
7
JUNCTION
RF1K49224
CTHERM1 7 6 1.00e-7
CTHERM2 6 5 9.00e-4
CTHERM3 5 4 3.00e-3
CTHERM4 4 3 4.00e-2
CTHERM5 3 2 5.20e-3
CTHERM6 2 1 1.90e-2
RTHERM1
CTHERM1
6
RTHERM1 7 6 7.10e-2
RTHERM2 6 5 1.90e-1
RTHERM3 5 4 5.95e-1
RTHERM4 4 3 4.27
RTHERM5 3 2 1.2e1
RTHERM6 2 1 1.04e2
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
9-29