AOT500L N-Channel Enhancement Mode Field Effect Transistor General Description AOT500 uses an optimally designed temperature compensated gate-drain zener clamp. Under overvoltage conditions, the clamp activates and turns on the MOSFET, safely dissipating the energy in the MOSFET. The built in resistor guarantees proper clamp operation under all circuit conditions, and the MOSFET never goes into avalanche breakdown. Advanced trench technology provides excellent low Rdson, gate charge and body diode characteristics, making this device ideal for motor and inductive load control applications. Standard Product AOT500 is Pb-free (meets ROHS & Sony 259 specifications) Features VDS (V) = Clamped ID = 80A (VGS = 10V) RDS(ON) < 5.3 mΩ (VGS = 10V) D D 10Ω G S D G S Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Symbol Drain-Source Voltage VDS Gate-Source Voltage VGS TC=25°C Continuous Drain Current G Units V clamped V 80 TC=100°C ID 57 Continuous Drain Gate Current IDG +50 Continuouse Gate Source Current IGS +50 Pulsed Drain Current C IDM 250 H A mA A Avalanche Current L=100uH IAR 50 A Repetitive avalanche energy H TC=25°C EAR 125 mJ Power Dissipation B 115 PD TC=100°C Junction and Storage Temperature Range 1/7 Maximum clamped TJ, TSTG Thermal Characteristics Parameter Maximum Junction-to-Ambient A Steady-State Maximum Junction-to-Case B Steady-State W 58 -55 to 175 Symbol RθJA RθJC °C Typ Max Units 60 0.7 75 1.3 °C/W °C/W www.freescale.net.cn AOT500L N-Channel Enhancement Mode Field Effect Transistor Electrical Characteristics (TJ=25°C unless otherwise noted) Symbol Parameter STATIC PARAMETERS BVDSS(z) Drain-Source Breakdown Voltage Conditions Min ID=10mA, VGS=0V 33 BVCLAMP IDSS(z) Drain-Source Clamping Voltage Zero Gate Voltage Drain Current ID=1A, VGS=0V 36 BVGSS Gate-Source Voltage VDS=0V, ID=250µA IGSS Gate-Body leakage current VDS=0V, VGS=±10V Typ VDS=16V, VGS=0V VGS(th) Gate Threshold Voltage VDS=VGS, ID=250µA 1.5 On state drain current VGS=10V, VDS=5V 250 RDS(ON) Static Drain-Source On-Resistance gFS Forward Transconductance VDS=5V, ID=30A 95 VSD Diode Forward Voltage IS=1A, VGS=0V 0.7 IS Maximum Body-Diode Continuous Current Crss Reverse Transfer Capacitance Rg Gate resistance 2 V 30 µA V 10 µΑ 3 V A 4.1 TJ=125°C DYNAMIC PARAMETERS Ciss Input Capacitance Output Capacitance 44 20 VGS=10V, ID=30A 5.3 6.2 VGS=0V, VDS=0V, f=1MHz mΩ S 4200 VGS=0V, VDS=15V, f=1MHz Units V ID(ON) Coss Max 1 V 80 A 5500 pF 765 pF 340 pF Ω 13 30 SWITCHING PARAMETERS Qg(10V) Total Gate Charge 69 89 Qg(4.5V) Total Gate Charge 34 nC 12 nC 15 nC 25 ns VGS=10V, VDS=15V, ID=30A Qgs Gate Source Charge Qgd Gate Drain Charge tD(on) Turn-On DelayTime tr Turn-On Rise Time tD(off) Turn-Off DelayTime tf trr Turn-Off Fall Time Body Diode Reverse Recovery Time IF=30A, dI/dt=100A/µs 60 Qrr Body Diode Reverse Recovery Charge IF=30A, dI/dt=100A/µs 84 VGS=10V, VDS=15V, RL=0.5Ω, RGEN=3Ω nC 35 ns 150 ns 62 ns 78 ns nC A: The value of R θJA is measured with the device in a still air environment with TA =25°C. B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C. D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient. E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max. F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of TJ(MAX)=175°C. G. The maximum current rating is limited by bond-wires. 11 H. EAR and IAR are based on a 100uH inductor with Tj(start) = 25C for each pulse. Rev 2: Dec 2010 2/7 www.freescale.net.cn AOT500L N-Channel Enhancement Mode Field Effect Transistor TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 250 100 10V 7V 200 5V 6V VDS=5V 4.5V 150 80 60 ID(A) ID (A) 4V 100 40 VGS=3.5V VGS=10V, ID=30A 25°C 125°C 50 20 0 0 -40°C 0 1 2 3 4 5 1 VDS (Volts) Fig 1: On-Region Characteristics 1.5 2 2.5 3 3.5 4 VGS(Volts) Figure 2: Transfer Characteristics 2 5 Normalized On-Resistance VGS=10V RDS(ON) (mΩ ) 4.5 4 3.5 3 1.8 VGS=10V ID=30A 1.6 1.4 20 48 30 10 1.2 1 0.8 26 63 40 13 0.6 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 150 175 200 Temperature (°C) Figure 4: On-Resistance vs. Junction Temperature ID (A) Figure 3: On-Resistance vs. Drain Current and Gate Voltage 14 100 ID=30A 10 12 1 IS (A) RDS(ON) (mΩ ) 10 8 125°C 125°C 0.1 25°C 0.01 6 0.001 4 25°C 0.0001 -1. -1. -1. -1. -0. -0. -0. -0. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 6 4 2 0 8 6 4 2 2 2 5 8 11 14 17 20 VGS (Volts) Figure 5: On-Resistance vs. Gate-Source Voltage 3/7 -40°C VSD (Volts) Figure 6: Body-Diode Characteristics www.freescale.net.cn AOT500L N-Channel Enhancement Mode Field Effect Transistor TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 7000 10 VDS=30V ID=30A 6000 Ciss 6 4 VGS=10V, ID=30A Capacitance (pF) VGS (Volts) 8 5000 4000 3000 2000 Crss Coss 2 1000 0 0 0 10 20 30 40 50 60 Qg (nC) Figure 7: Gate-Charge Characteristics 70 0 15 10000 1ms 10 30 TJ(Max)=175°C TA=25°C 20 48 30 10 1000 10ms TJ(Max)=175°C TC=25°C 26 63 40 13 DC 1 0.1 25 10µs RDS(ON) limited 100µs 1 10 100 VDS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note E) 10 Zθ JC Normalized Transient Thermal Resistance 20 Figure 8: Capacitance Characteristics Power (W) ID (Amps) 10 VDS (Volts) 1000 100 5 100 0.00001 0.0001 0.001 0.01 0.1 1 Pulse Width (s) Figure 10: Single Pulse Power Rating Junctionto-Case (Note F) In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse D=Ton/T TJ,PK=TC+PDM.ZθJC.RθJC RθJC=1.3°C/W 1 0.1 PD Single Pulse 0.01 0.00001 0.0001 0.001 Ton 0.01 0.1 T 1 10 100 Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance (Note F) 4/7 www.freescale.net.cn AOT500L N-Channel Enhancement Mode Field Effect Transistor TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 120 L ⋅ ID tA = BV − V DD 100 100 VGS=10V, ID=30A Power Dissipation (W) ID(A), Peak Avalanche Current 1000 80 60 40 20 TC=25°C 0 10 10 100 1000 Time in avalanche, tA (us) Figure 12: Single Pulse Avalanche capability 0 25 50 75 100 125 150 TCASE (°C) Figure 13: Power De-rating (Note B) 175 100 Current rating ID(A) 80 60 40 20 0 0 25 50 75 100 125 150 175 TCASE (°C) Figure 14: Current De-rating (Note B) 5/7 www.freescale.net.cn AOT500L N-Channel Enhancement Mode Field Effect Transistor TYPICAL PROTECTION CHARACTERISTICS 2.00 Trench BV ID (A) 1.50 BVCLAMP 1.00 0.50 D BVDSS(Z) 0.00 R 30 35 40 45 It can also be said that the VDS during clamping is equal to: BVDSS = BVCLAMP + VGS(PLATEAU) Additional power loss associated with the protection circuitry can be considered negligible when compare to the conduction losses of the MOSFET itself; + - VPLATEAU S - 60.00 BVCLAMP25oC 50.00 ID (A)/ Vds(V) VGS(PLATEAU)= 10Ω x 300mA =3V + G VDS (Volts) Fig 15: BVCLAMP Characteristic This device uses built-in Gate to Source and Gate to Drain zener protection. While the Gate-Source zener protects against excessive VGS conditions, the Gate to Drain protection, clamps the VDS well below the device breakdown, preventing an avalanche condition within the MOSFET as a result of voltage over-shoot at the Drain electrode. It is designed to breakdown well before the device breakdown. During such an event, current flows through the zener clamp, which is situated internally between the Gate to Drain. This current flows at BVDSS(Z), building up the VGS internal to the device. When the current level through the zener reaches approximately 300mA, the VGS is approximately equal to VGS(PLATEAU), allowing significant channel conduction and thus clamping the Drain to Source voltage. The VGS needed to turn the device on is controlled with an internally lumped gate resistor R approximately equal to 10Ω. + Vz - 40.00 30.00 BVCLAMP 100oC 20.00 10.00 0.00 0.00E+00 2.50E-06 5.00E-06 7.50E-06 1.00E-05 Time in Avalanche (Seconds) Fig 16: Unclamped Inductive Switching EX: 6/7 PL=30µAmax x 16V=0.48mW (Zener leakage loss) PL(rds)=102A x 6mΩ=300mW (MOSFET loss) Fig16: The built-in Gate to Drain clamp prevents the device from going into Avalanche by setting the clamp voltage well below the actual breakdown of the device. When the Drain to Gate voltage approaches the BV clamp, the internal Gate to Source voltage is charged up and channel conduction occurs, sinking the current safely through the device. The BVCLAMP is virtually temperature independent, providing even greater protection during normal operation. www.freescale.net.cn AOT500L N-Channel Enhancement Mode Field Effect Transistor Gate Charge Test Circuit & Waveform Vgs Qg 10V + + Vds VDC - Qgs Qgd VDC - DUT Vgs Ig Charge Resistive Switching Test Circuit & Waveforms RL Vds Vds DUT Vgs 90% + Vdd VDC - Rg 10% Vgs Vgs td(on) tr td(off) ton tf toff Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L 2 EAR= 1/2 LIAR Vds BVDSS Vds Id + Vdd Vgs Vgs I AR VDC - Rg Id DUT Vgs Vgs Diode Recovery Test Circuit & Waveforms Q rr = - Idt Vds + DUT Vgs Vds - Isd Vgs Ig 7/7 L Isd + Vdd t rr dI/dt I RM Vdd VDC - IF Vds www.freescale.net.cn